A frequency divider circuit having master-slave type flip-flop binary circuits formed from complementary insulated gate field effect transistors. Presetting means incorporated in one of the master or slave flip-flop circuits, the clock signal for the flip-flop circuit not having said presetting means is adapted so that said flip-flop circuit is subordinate to the flip-flop circuit incorporating the presetting means during the presetting operation.
An improved CMOS frequency divider circuit is disclosed which has override logic for forcing the circuit to exit from a forbidden state to a valid state.
A presettable dynamic delay flip-flop circuit including two first and second series-connected 1/2 bit delay circuits, a gate circuit for supplying these delay circuits with a control signal for controlling their operation, and a switching circuit for supplying the second delay circuit with preset data capable of freely presetting the voltage level of an output signal from said flip-flop circuit. The delay circuits and switching circuit are respectively formed of clocked inverters. The flip-flop circuit is formed of a small number of elements and operated at high frequency.
A first circuit is made up of a first clocked inverter and a first modified clocked inverter. A second circuit is made up of a second clocked inverter and a second modified clocked inverter. The first circuit has substantially the same circuit arrangement as that of the second circuit. The first circuit operates in response of the output signal from the second circuit, and vice versa.
A resettable D type flip flop for integrated circuit counter circuits, which flip flop comprises master and slave flip flop stages. The slave flip flop stage includes NOR and an INVERTER circuit selectively coupled via a first transmission gate to form a latch or via a second transmission gate to accept new data. The master flip flop stage having an output terminal coupled to apply signal to the slave includes a NOR circuit having an input and its output terminals directly connected to the output and input terminals respectively of a second INVERTER circuit. The NOR is selectively energized to complete a latch circuit or inactivated to permit input data to be applied to an interconnection at its output terminal via a third inverter having an input connected to a DATA input terminal for receiving input signal and which third INVERTER is selectively energized to render it alternately active and inactive.
A binary counter provided with complementary field effect transistor inverters which includes at least three complementary field effect transistor inverters, at least two of which comprise clocked inverters acting upon receipt of clock signals having a complementary relationship. The three inverters are cascade connected with the output terminal of the last stage inverter connected to the input terminal of the first stage inverter, and the two clocked inverters are made to act alternately upon receipt of complementary clock signals, thereby enabling an output to be generated from the output side of one of the inverters with a frequency equal to half that of clock signals simultaneously supplied to both clocked inverters.
