A correlator comprising a plurality of sets of multivibrators, each set bg serially connected to form a shift register, each multivibrator having a set and a reset output lead, indicating its binary state. The plurality of shift registers comprise a J number of signal shift registers and, in the simplest embodiment, one reference shift register. Each multivibrator is connectable to a clocking source for shifting the states of the multivibrators. One of the multivibrators of each set, at one end of the series, the input multivibrator, is connectable to a source of signals, generally bilevel signals or pulses, each pulse having a predetermined time duration or a multiple thereof. The binary states of the multivibrators of the reference shift register, whether stationary or shifting with the incoming stream of bits, may be added to the binary states of corresponding multivibrators of the signal shift registers. Means are operatively connected to the output leads of corresponding multivibrators for summing the outputs of the multivibrators for each shift of binary states, the sum being a maximum for a particular combination, or coding, of binary states of the multivibrators of the shift registers. The means may comprise a plurality of modulo-2 adders, one for each of the multivibrators of the signal shift registers, and the same number of output resistors. The specific combination of connections are chosen in a manner so that, with applied input signals to the input multivibrators, a particular combination of binary states of the multivibrators will result in a maximum total output signal.
An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes. A data shift register receives input data and loads the input data. A reference shift register receives reference data and loads and circulates the reference data. A pulse correlator connected to the shift register and the reference shift register correlates the input data with the corresponding reference data and provides a pulse correlator output. An accumulator connected to the pulse correlator receives and adds the pulse correlator outputs from the correlation processes to produce a correlator output corresponding to the predetermined number of correlation processes.
A variable tap weight convolution filter comprised of charge transfer devices which may be charge coupled devices, bucket brigade devices or a combination of the two, for performing convolutions of an input signal with tap weights from a second input signal, said tap weights varying as a function of time.
A digital m of n correlation device using signal and reference shaft registers, modulo 2 adders, unique 1-bit D/A converters, and single resistor analog summing provides a very fast correlation product for pulse compression modulations such as phase or frequency shift keying. The compression ratio for the digital m of n correlation device, according to the present invention, is 168:1 (equal to the number of bits). The device is capable of bit rates in excess of 100 Mbps and is well suited for LSI fabrication.
Circular correlator/convolver for discrete sample signals having a first shift register to receive the sample signals in series and a second shift register to receive the sample signals, in parallel, from the first register to circulate these signals in the second register, and once each shfit period, to apply the n signals it is storing to a group of n multipliers, Each multiplier receives also a second signal which serves as a second operand and is multiplied with the signal received from the second shift register. The correlated/convolved values are produced in response to the product signals generated by the multipliers during the time a following group of sample signals is being read into the first shift register. The design is suitable for implementing with charge-coupled devices on a single substrate.
An analog output circuit for a digital correlator that may be completely integrated with the digital correlator on a single CMOS/LSI chip. The output circuit includes a compensating arrangement so that its output voltage is substantially unaffected by internal processing variables between different chips or by external variables such as temperature or supply voltages. The circuit includes a reference MOS unit and a correlation MOS unit each including parallel arranged PMOS transistors respectively coupled in series with first and second NMOS transistors. An operational amplifier biased to a voltage V.sub.REF is coupled between the reference MOS unit and the gates of the first and second NMOS transistors. The circuit operates to bias the gate of the second NMOS transistor so that constant output voltage steps are provided in the series path between the correlation MOS unit and the second NMOS transistor as long as variations of operating parameters track each other uniformly between the PMOS units and between the NMOS transistors.
