A system for storing waveforms in which each waveform is converted to digital data and stored in a memory sector under the control of a history controller to select the sector and memory counter to select the individual address locations in each sector. When the memory capacity is exceeded, the oldest waveform data is replaced by the newest.

A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radicies selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input data state satisfying a selected count-qualifier state condition.

An electrocardiograph which includes a detecting circuit for detecting a cardiographic signal from a living body; a storage circuit for storing the cardiographic signal from the detecting circuit; a storage control circuit capable of performing a storage control operation in such a way as to sequentially and continuously store a new cardiographic signal in the storage circuit for the formation of cardiographic data and as to successively erase old cardiographic data which are stored in the storage circuit; and a cardiographic data hold commanding circuit operable in response to a cardiographic data hold commanding signal to command the retaining of cardiographic data in the storage circuit.

A logic state analyzer monitors an ongoing succession of logic states occurring in a collection of n-many digital signals, and stores in a memory a set of logic states selected from the ongoing succession. A logic state is any one of the 2.sup.n -1 possible patterns the n-many digital signals may exhibit. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored logic states are overwritten as the newest logic states are stored. Various storage qualification criteria may be specified, in which case an individual logic state is not stored unless it meets those criteria. Upon recognition of a specified trigger condition in the succession of logic states the logic state analyzer stores an operator selectable number of additional logic states, after which the monitoring and storing of logic states ceases and the stored contents of the memory are displayed. The trigger condition may be the detection of a designated sequence of selected logic states. A sequence detector monitors the ongoing succession of logic states. To satisfy the sequence and thus meet the trigger condition the first logic state in the sequence must occur and be subsequently followed by the next logic state in the sequence, and so on, until all selected logic states in the designated sequence have occurred. It may also be required that each logic state in the sequence be detected a selected number of times before an occurrence of the next logic state in the sequence can contribute toward satisfaction of the sequence. A logic state may be designated as a restart state whose occurrence nullifies any partial satisfaction of the sequence and causes the process of sequence satisfaction to begin afresh.

A logic state analyzer monitors the ongoing succession of states occurring in a collection of digital signals, and stores in a memory either all such states or a selected subset thereof meeting certain qualification criteria. The oldest stored states are overwritten as the newest states are stored. Upon recognition of some trigger condition the logic state analyzer will subsequently store a preselected number of additional states, the collectivity of which may be termed the captured trace. The utility of such a trace in a logic state analyzer is enhanced by equipping the analyzer with a counting mechanism selectively responsive to a high speed clock signal or a programmable state detector. In the former case the counter operates as a timer whose value may represent either the elapsed time between consecutive states in the trace or between each state in the trace and an origin along a time axis. In the latter case the user identifies a state or event of interest and the counter records the number of times that state occurs between the stored states of the trace. In both cases the values of the times or event counts are stored as part of the trace and are displayed in correlated relation to the state data therein.