A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.

Disclosed is an analog multiplexer in which a plurality of emitter follower differential amplifiers formed of several pairs of bipolar transistors connected in parallel with each other are connected in common to one terminal of a power source through a current mirror load circuit, and to the other terminal of the power source via a switch circuit and a constant-current source. The switch circuit is to connect the constant-current source selectively to the common conjunction of the emitters of each pair of emitter follower differential amplifiers.

Multiplexers and demultiplexers including sampling gates in the form of diode bridges are disclosed. Plural-input gates, each formed from two or more diode bridges with two adjoining arms in common, are utilized in a multiplexer designed to synthesize a multi-level output train from a number of binary input trains exceeding the number of gates.

A dual bus driver including a voltage input, a current source, a single data input, a first driver transistor for driving one bus, a second driver transistor for driving the other bus, a first pair of differential transistors for turning on either the first driver transistor or the second driver transistor to couple an input signal at the data input to the one bus or the other bus, and a second pair of differential transistors for disabling both driver transistors. By providing a driver that drives both buses, reduced power consumption, fewer circuit components and less integrated circuit layout complexities are achieved.

A data arbitration apparatus for combining data from a plurality of data paths, wherein data from the respective data paths are clocked by respective clock signals asynchronously and at different rates includes a multiplexer to which the respective data paths are coupled. The output of the multiplexer is applied to a "D"-type register having a dock input terminal coupled to one of the respective clock signals. The D-type register provides the combined data signal. A logic arrangement is coupled to the respective clock signals for providing control signals according to a hierarchy of importance of the signals occurring on the respective data paths. The control signals are coupled to condition the multiplexer to provide data samples from the respective data paths according to the established hierarchy. The logic arrangement is constructed such that the multiplexer switches to a different data path on a predetermined transition of the clock signal for that data path and switches back to the prior connected data path on the next predetermined transition of the clock signal associated with such prior connected data path.