An adjustable circuit for an electronic timepiece including a crystal oscillator, a frequency divider circuit, a display and a controlable means for increasing and decreasing the output frequency of the frequency divider circuit. The increasing and decreasing means includes a digital adder and a digital subtractor and a plurality of controlable gates for enabling the digital adder or subtractor to increase or decrease the output frequency of the frequency divider.

A time indication setting circuit for accelerating or stopping the advance of the time indicating mechanism in an electronic timepiece. A delay circuit receives time pulses developed within the timepiece and the time pulses and delayed time pulses from the delay circuit are applied to a gate circuit. The gate circuit applies the time pulses and the delayed time pulses, under the control of a control circuit, to the timepiece drive train to drive the timepiece time indicating mechanism at a rate determined by the pulse repetition rate of the pulses applied to the drive train. The control circuit is manually operable to apply the control signal so the gate circuit applies both the time and the delayed time pulses to the drive train and thereby accelerates the advance of the time indicating mechanism, or to block both the time and the time indicating pulses and thereby stop the advance of the time indicating mechanism or to apply only the time pulses to the drive train so that the time indicating mechanism advances at a normal rate.

A rotate switch mechanism for actuating time correction displayed by an electronic timepiece comprising a rotatable crown and stem, a toothed wheel rotatably connected to the stem and a switch assembly. The switch assembly contains a switch blade precisely positioned within the periphery of the teeth of the toothed wheel and deflected thereby, with rotation of the crown, to make contact with either of two switch contacts. Circuitry responsive to each switch closure is provided for incrementally effecting time correction, forward and backward, with clockwise and counterclockwise rotation of the crown, respectively.

A solid state digital watch comprises a stem detent and switch assembly which includes a crown portion on the outside of the watch case and a shaft portion extending therethrough. The shaft portion includes an intermediate rectangular section on the inside of the case which cooperates with a single stamped spring to provide a four position rotary detent action. In addition to permitting detent holding of the stem in the proper contact position, this arrangement also provides electrical contact to ground the stem to the case. The internal end of the shaft includes an eccentric tab which contacts one of three precisely positioned blades when the stem is rotated to advance the minutes or hours counters, to reset the seconds counter or to shut down the watch.

The time correction circuit comprises a switch, a first shift register circuit including two cascade connected shift registers driven by a 32 Hz clock pulse for shifting an electric signal generated by the operation of the switch, a second shift register circuit connected to the first shift register circuit and including two cascade connected shift registers driven by 1 Hz clock pulse for detecting the fact that whether the switch is maintained operated for an interval longer than a predetermined interval or not, a NOR gate circuit connected to receive the output from the two shift registers of the first shift register circuit, an AND gate circuit connected to receive the output signals from the first and second shift register circuits and a clock pulse having a predetermined frequency and an OR gate circuit connected to receive the output signals from the NOR gate circuit and the AND gate circuit.