The differential amplifier current folder and coder circuit of the present invention is dynamically biased in accordance with the magnitude of the input signal to the differential amplifier. The biasing current through the main coding paths of the folder circuitry is thus reduced for lower magnitude input signals, and the coding error introduced due to resistor variations (i.e., I.DELTA.R voltage drops) and transistor base currents varies in accordance with the magnitude of the input signal rather than remaining a constant due to the presence of a constant biasing current. Lower magnitude input signals can thus be coded with a minimum of error using either thin film techniques or components readily available from commercial sources.
A limiter circuit comprises circuit means for variably controlling a current source for a differential amplifier in accordance with the magnitude of a modulating signal carried by a carrier or a percentage modulation.
A switching array comprising low power switching elements for switching high bandwidth pulse encoded signals with minimum distortion. Each switching element comprises an emitter-coupled pair of transistors which are used to switch the pulse encoded signals. The pair of transistors are enabled and disabled by inhibiting the flow of electrical current through the latter. A transistorized switch controls the electrical current in the pair of transistors in response to signals from a control register within the switching array. Since no current is flowing in the pair of transistors when the element is inhibited, the power dissipation approaches zero in the inhibit state resulting in an overall low power dissipation for the switching array since only a small number of elements are normally enabled at any time. Each element further comprises an emitter-follower transistor for the purpose of isolating the pair of transistors from the remainder of the switching array in order to reduce the crosstalk between pulse encoded signals.
A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.
A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
