Disclosed is a read clock generator for use in a semiconductor memory. The read clock generator is comprised of a bistable amplifier and a differential voltage sensor. The bistable amplifier is activated during a read cycle; and it simulates the transient operation of a plurality of sense amplifiers which sense binary information stored within the memory. The differential voltage sensor couples to the bistable amplifier, and produces an output signal when the bistable amplifier stabilizes.

A 1,024 bit semiconductor memory system, fabricated on a single integrated circuit chip, utilizes dynamic memory cells and low power dynamic control circuitry. An initial input control signal activates the control circuitry which internally generates all the control signals. The timing of all the internally generated control signals is automatically maintained by the control circuits.

An on-chip reference voltage source is coupled to an on-chip integrated circuit such as a memory cell. The reference voltage is compared against internal signals generated by the on-chip integrated circuit in order to develop an output voltage representing the state of the integrated circuit. In memory applications the memory reference signal constitutes a threshold voltage which is compared against the internal voltage logic swing generated by one half of the memory cell for providing output signals indicative of the state of the memory cell. Selecting the impedance of the reference voltage source and the integrated circuit (one half the cell in memory applications) to be identical from an electrical and device standpoint allows lower threshold noise levels to be used despite the existence of process, impedance (AC and DC), temperature and input signal variations. This permits power savings, and increased densities.

A circuit arrangement for monitoring the function of a dynamic decoder circuit which comprises at least parallel-connected decoder transistors, a pre-charging transistor, and an end stage which samples the output signal of the decoder transistors, is disclosed in which for simulating the decoder circuit, two discharge transistors are connected in parallel and have control inputs which are supplied with address signals in inverted form and in non-inverted form and whose node, which is formed by the one connection point, is precharged in that it is connected to a further transistor. In order to simulate the capacitance existing at the corresponding connection point of the parallel-connected decoder transistors of a decoder circuit, a varactor is connected to the node and the node is also connected to the further circuit elements provided in the decoder circuit between the decoder transistors and the end stage. For simulating the capacity load formed by the end stage of the decoder circuit, a further varactor is provided which is subsequently connected to the further circuit elements.

A static random access memory which generates a memory status signal for improved performance. The same signal in a random access memory which enables data to go to the output is taken to form the leading edge of a memory status signal, indicating that output data is available. The trailing edge of the pulse, indicating a memory readiness condition, is formed upon completion of memory preset. The memory status signal tracks variations in performance of the data storage cells due to voltage, temperature and other processing variables, thus permitting access of data when data is actually available for reading, rather than on worst case considerations.