An associative array of memory cells is arranged with its read cells interleaved with its storage cells to reduce the physical space required by the array. Two rows of read cells have four rows of storage cells on each side thereof except that the uppermost row of the read cells in the array has only two rows of the storage cells thereabove and the lowermost row of the read cells in the array has only two rows of the storage cells therebelow. One half of the read cells in each row of the read cells provides an output for one of the two adjacent rows of the storage cells.
An arrangement for reducing the access time (increasing the hit rate) by the intermediate storage of a plurality of items of data read out from a working store in a storage system with a working store which is divided into storage modules employs the division of each working store module into a plurality of storage zones which can be read out independently of one another. Instead of providing a common data input and output register for the entire storage module, each storage zone is assigned its own read-out data register and the entire storage module is assigned a common data write-in register.
A memory device is provided with first and second memories. Two groups of data are loaded into the first and second memories, through a data buffer register. The same address information is applied to the first and second memories and the information is read out from the first and second memories. The two groups of the data read out in parallel are applied to a data multiplexer which in turn converts the parallel information into the serial one.
A digital computer memory made up of a plurality of read only memory components arranged in a matrix of rows and columns. The outputs of the columns of memory components are connected to a voltage source and load resistors to provide the output terminals of the memory. Sets of digital words having at least a field or portion of a field with bits represented by the same logical state are grouped in such memory so that, when a word in such set is addressed, the bits in such field are produced at the output terminals by the volage source and load resistors. With such arrangement the number of read only memory components required in such memory is reduced.
An improved CAM (content addressable memory) cell is provided with dual address lines operable independently for a Read operation or for a Write operation. The cell is additionally provided with dual ports so that the first port permits a data input for Write operations or alternatively a data input for Search-Compare operations. The second port (Data Output) is independently connected to enable Read out of data residing in the cell. Each CAM cell also has a coincidence line (match-hit) output to indicate when an input Search bit or word coincides with resident data within the CAM cell. The CAM cells are arranged in an array of "m" rows with each row having "n" bits to hold a "n" bit word. Operationally the array permits both "Read" and "Search-Compare" operations to be accomplished in one clock cycle rather than the usual requirement of 3-4 clock cycles.
A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.
