Characteristics of photolithographically-defined planar semiconductor device pairs made from the same master are different, but many of the differences are regular in kind. To achieve a device pair in which the magnitude of the difference in the characteristics of the elements of the pair is reduced, two pairs are made from the same master. The first element of one pair is connected to the second element of the other pair so that the two operate as one composite element. The second element of the one pair is connected to the first element of the other, similarly for operation as another composite element the characteristics of which closely match those of the one composite element.
An alignment check pattern formed by a first insulating film; a first dummy pattern formed on a surface of said first insulating film; a second insulating film formed on a composite surface of said first insulating film and said first dummy pattern; a second dummy pattern formed on said second film, and positioned directly over said first dummy pattern in plan view; a third insulating film formed on a composite surface of said second insulating film and said second dummy pattern; a regular scale pattern formed on said third insulating film, and positioned directly over said second dummy pattern; fourth insulating film formed on a composite surface of said third insulating film and said regular scale pattern; and a vernier scale pattern formed on a surface of said fourth insulating film and positioned directly over said regular scale pattern.
A method and apparatus for providing a mask (200) on a multi-site wafer (100) is accomplished by first creating a first mask key (204) which contains information, such as alignment cues and test structures. A copy of the first mask key is modified to produce a second mask key (201). When the two mask keys are transferred to adjacent sites on the wafer, they physically overlap, preventing double-exposure of the information in the first mask key.
An integrated circuit includes a plurality of circuit elements interconnected to operate as a circuit and formed in a common semiconductor substrate. The substrate is mounted on a supporting package, resulting in a mechanical stress in the substrate which is symmetrical about at least one given axis. At least the circuit elements with operating characteristics which are altered by the mechanical stress and which have a critical matching or ratio relationship are arranged symmetrically about the stress axis of symmetry. In a preferred form, the integrated circuit is a linear circuit, such as an operational amplifier employing junction field effect transistors (JFETs) for its input stage and bipolar transistors for its amplifier stage. Providing device symmetry about an axis of mechanical stress symmetry enables shifts in input offset voltage for such operational amplifiers to be reduced up to a factor of about 10.
