A data acquisition system capable of resolving transient pulses in the subnanosecond range. A pulse in an information carrying medium such as light is transmitted through means which disperse the pulse, such as a fiber optic light guide which time-stretches optical pulses by chromatic dispersion. This time-stretched pulse is used as a sampling pulse and is modulated by the signal to be recorded. The modulated pulse may be further time-stretched prior to being recorded. The recorded modulated pulse is unfolded to derive the transient signal by utilizing the relationship of the time-stretching that occurred in the original pulse.

A method of producing optical and electrical pulses of desired shape. An optical pulse of arbitrary but defined shape illuminates one end of an array of optical fiber waveguides of differing lengths to time differentiate the input pulse. The optical outputs at the other end of the array are combined to form a synthesized pulse of desired shape.

A matrix multiplier system incorporating an integrated fiber optic coupling array in combination with an arrangement for individually modulating the signals on the respective optical fiber transmission lines to develop the matrix multiplication. Each of the individual couplers accomplishes the coupling of an input signal into a bi-directional fiber optic transmission line with high efficiency and unilateral coupling effect. The signal thus coupled into the bi-directional transmission line is reflected back to the coupler output after multiplication by the modulating vector component for the individual coupler element. Because of the fabrication of a large number of identical fiber optic couplers in a compact, integral array and the manner in which the light signals can be modulated, the matrix multiplier system is extremely effective in pattern recognition, signal discrimination, selected signal enhancement, and the like.

Microcomputer system providing time management enabling control and acquisition of data indicative of condition changes occurring at high speed. The system comprises a memory plane with associated address decoders and interface circuits which define a switched register zone operably coupled to a memory control logic and a processor via the interface circuits and temporally shiftable therebetween. An address generator is connected to the switched register zone and provides respective addresses thereto in response to an access by the memory control logic. A time base circuit is connected to the switched register zone and to a sequencer which is likewise connected to the switched register zone. An action unit controlled by the time base circuit decodes control commands from the switched register zone. An input unit upon detecting a change of condition (e.g. in an operating engine) generates a capture request signal to the address generator. An output unit controlled by the time base circuit and connected to the action unit produces outputs with time delays, thereby desequencing the outputs. The switched register zone and the time base circuit interact with the input unit to provide an acquisition function and with the output unit to provide a control function. A serial interface driven by the time base circuit provides data reception and transmission functions, and an interrupt unit accepts interrupt requests originating from the programmable control function, the programmable acquisition function or from the serial interface and places the interrupt requests in a dynamic priority hierarchy.