A repeat is performed in a computer system after detection of an error in the operation, the circumstances then being changed as much as possible. The clock frequency is then decreased by the selective blocking of a part of the clock pulses, so that second clock pulse cycles are produced which are composed of the same but wider spaced clock pulses. All functions remain possible duringthe second clock pulse cycles, be it at a lower speed. The circumstances can be further modified yet by first completely stopping the computer system for a given period of time, or by erasing the information sorted in a foreground store.
A digital computer monitoring and restart circuit monitors the presence of periodic output signals from the digital computer by a missing pulse detector. When the detector senses a missing output signal from the computer, it indicates this detection operation by an output signal representation of the fact that the computer is not operating. In response to this output signal a restart pulse is generated by a restart pulse generator and is applied to the computer to restart the computer and to reset the monitoring circuit. Concurrently, a 5-second timer circuit is started. While the timer circuit is operating over its 5-second interval, if the monitoring circuit produces another output signal indicating that the computer is not operating, the 5-second timer is stopped and another restart operation is not attempted. If the 5-second timer is allowed to run to the end of the 5-second interval without the detection of a computer outage, the monitoring and restart circuit is reset by the 5-second timer to an initial state indicative of the continuing operation of the computer while awaiting a subsequent computer outage.
Apparatus and method are provided for isolating errors in a logic system employing memory and having a data transmission bus structure. A memory readout error is detected in a multibit word having a parity bit added thereto by parity checking means. A readout error, commonly referred to as a "soft read error," is an erroneous output from a memory device that is transient in nature in that the soft read error is corrected when the memory device is refreshed or reread. It is contemplated that such a readout error may take place when a multibit word is outputted from a refresh type random access memory such as a dynamic random access memory (RAM) or a write after read core memory. In response to the detection of an error condition in the memory by the parity bit error detector, the memory is read again in order to obtain a second output. If the second output provided by the memory does not contain a parity error, the prior error is considered to be a soft read error and the second data word is forwarded to a utilization device such as a CPU. If the second output from the memory also contains a parity error, such an error is considered to be a "hard read error" and the data is not utilized. Information relating to a parity error occurring in the memory which is not a soft read error is stored for diagnostic purposes. Parity of the data is again checked at the utilization device in order to determine if the transmission means used to transfer the data from the memory to the utilization device has caused a data error. Means of inducing parity errors to test the parity detection circuitry and means to override parity checking are also provided.
A minicomputer comprises a microprogrammable central processing unit wherein micro-instruction execution speed is optimized through the use of variable micro-instruction timing logic and by grouping micro-instruction according to execution time. Furthermore, data paths are arranged so that micro-routines that implement more complex operations, i.e., memory reference instructions, follow the fastest route possible. When micro-instructions requiring longer data paths are programmed, the computer dynamically varies the length of the microcycle to be a function of both the type of micro-instruction to be executed and the state of the minicomputer when the micro-instruction is to be executed. A microprogrammable processor port is provided to allow coupling of external hardware, e.g., I/O devices, other processors, etc., directly to the microprogrammed control processor. This capability is in addition to the standard input/output system of the minicomputer, thereby providing an alternate interface path for devices requiring very fast transfer rates. These devices interfaced through the microprogrammable processor port are directly coupled to the internal data busses of the minicomputer and addressed under direct microprogram control as if they were internal processor registers. Block transfers of data are provided via this microprogrammable port to allow transfers of large blocks of data without dependence on the I/O system timing of the minicomputer. A remote program load feature is provided whereby an I/O device or data communications interface can initiate a bootstrap operation in a remote computer, i.e., the computer can be halted, a preselected ROM loader program is transfer into memory, all input/output instructions in the loader are automatically configured to the proper select code of the I/O device, and the computer is restarted at the proper loader program starting address.
The present invention relates to a slow down circuit for use with a digital computer having a microprocessor ready line, an address bus and a data bus. The slow down circuit is comprised of an address decode logic unit for producing an inhibit signal when predetermined bit patterns appear on the address bus. The predetermined bit patterns represent special computer functions which require the computer to operate at normal speed. A slow down signal generator is connected to the address bus and the data bus for generating a bi-level signal. A combiner is connected to the address decode logic unit and the slow down signal generator for combining the inhibit signal and the bi-level signal to produce a control signal. The control signal has a first and a second logic level. When the control signal is at the first logic level the computer operates at normal speed. In the absence of a special function the control signal alternately switches between the first logic level and the second logic level causing a disabling of the microprocessor to thereby slow down the operation of the microprocessor.
A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.
