A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a delay by the second delay circuit, whereby the output signal is made apparently free from the delays due to the preceding stage or stages and to the memory and logical circuits.
This relates to an MOS logic synchronizing circuit operating with a single phase clock waveform. A logic inverter has two parallel-connected switching MOST's, the gate of one (M4) being connected to clock and the gate of the other (M2) being coupled to the logic input via the source-drain path of a third MOST (M1) whose gate is connected to clock. Input signal change is delayed by a full clock period.
A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.
An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.
An MOS circuit synchronizes an asynchronous input signal to first and second alternating clock pulses in an integrated circuit system employing clocked ratio logic. A bistable device, such as a flip-flop, has first and second complementary inputs for establishing the state of the device and an output reflecting the state of the device. An input circuit for the bistable device receives the asynchronous signal and applies the signal to the first complementary input and the inverted asynchronous signal to the second complementary input. In addition, the input circuit has gate logic, implemented with field effect transistors, which decouples the asynchronous input for all intervals of time except during the interval of the first clock pulse. An output circuit for the bistable device employs an inverter in series with a field effect transistor which is driven into condition only during the interval of the second clock pulse. The MOS synchronizer circuit thus insures that an output signal of usable logic level is generated for an input signal occuring at any time with respect to the clock pulses of a clocked ratio MOS system.
