An electronic tester for testing an electronic structure having high circuit density, such as large scale integrated devices, system, and subsystem structures having a plurality of interconnected large scale integrated devices, and the like. The tester utilizes m words each containing n binary bits, where m is any integer in the range of one hundred through multiple thousands and n is any integer in the range of one hundred through multiple hundreds. The n binary bits of each word are respectively electrical manifestations employed by the tester to test the device under test. Where all, or a number, of said m words differ in content in one, or only a limited number of bit positions, only a complete one of said m words will be stored and only selected portions of the remaining similar words will be stored. Means is provided for reconstructing a discrete n binary bit word corresponding to each said stored selected portion of an n binary-bit word. Thus where m words each having n binary bits are required and certain of said m words differ from others of said m words in only a limited number of bits the practice of applicant's invention accomplishes a material reduction in the size of the store required.
A test mode setup circuit for a microcontroller unit (MCU) operates a test mode for an internal circuit or the like using only a reset pin and a clock pin, which are required pins. Thus, the microcontroller uses the test mode setup circuit without providing a separate test pin. The test mode setup circuit is suitable for an MCU having a small number of pins. In addition, various test modes for the microcontroller can be achieved by decoding a test mode count value of a test mode counter in alternative ways.
In automatic test equipment the logical levels on certain of the test pins are set to 0 and 1 by corresponding flip-flops included in respective I/O logic circuits. The states of the flip-flops (as well as other factors) are controlled by commands read out of a control RAM which is of sufficient width to provide a 4-bit command on lines for each logic circuit. The available commands include NOP commands and change commands which toggle the states of the corresponding flip-flops. A relatively small number of addresses of the control RAM have change commands entered in correspondence with selected ones of the pins. By repeatedly reading out the commands in these addresses in a non-cyclic sequence it is possible to generate a succession of different states of the flip-flops in the logic, which succession is much longer than the number of addresses of the control RAM which are utilized. Apparatus for establishing the correct addressing sequence is described.
Automatic testing of digital sequential logical devices employing a read y memory programmed with a series of inputs. The read only memory programmed outputs are then compared in EXCLUSIVE OR gates with the outputs of the device under test.
Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.
An apparatus for testing circuit board systems utilizing microprocessors which includes means for selectively exercizing each terminal or pin of the board system during each step of the testing protocol. Each step of the protocol can be preselected to operate according to an automatic sequence or according to a preprogrammed manner, or the apparatus may be conditioned to receive a response from the circuit board system at a selected terminal during a selected step of the testing protocol. The testing apparatus further includes an interactive interface to permit the board system under test to control the speed and sequence of the test procedure. The testing apparatus is capable of exercizing the board systems under test in a simulated environment at typically normal operating speeds so that degradation of system performance related to operational speed and other factors found in an operating environment can be analyzed.
