An adapter for use with a host processor for processing interrupts between a host processor and a plurality of remote data terminal devices is disclosed. The adapter includes a microprocessor, counter means which is incremented by a clock for sequentially interrogating a plurality of remote data terminal devices to determine whether or not a remote device is requesting access to the host processor and an external buffer for storing the output of the counter. The output of the counter is transferred to the microprocessor upon the sensing of a request signal for use by the microprocessor in identifying the requesting remote data terminal device and for processing the data from the requesting device to the host processor. The operation of the counter means is controlled by the microprocessor in accordance with the availability of the microprocessor to service the requesting data terminal device.

An interface for managing information exchanges on a communications bus between at least one control unit and peripheral units, or between said peripheral units. The exchanged information includes data and a destination address of said data. The interface is characterized in that it comprises for each unit, data transmission circuitry connected to the unit and to the bus for managing the data transmission on the bus to the unit having the destination address, data reception circuitry connected to the units and to the bus, for managing the reception of data by the unit having the destination address, and management circuitry for managing the addressing of the units during exchanges and in particular for managing access priorities to the bus, without necessitating the intervention of the control unit. This interface can be used for information exchanges between processing or measuring units.

A demand driven access mechanism comprises logic apparatus at each station capable of seizing use of the shared communication channel for enabling access by a selected single station. The logic apparatus receives status signals from all stations so that if one station seeks access to the channel it will be enabled. If two or more stations simultaneously seek access to the channel, the logic apparatus establishes a priority order between them, thereby enabling access to only one station at a time. The stations time-share the channel so that relatively slow stations may make more effective use of the relatively fast communication channel.

A refrigeration system contains a common compressor supplying refrigerant to a plurality of evaporators that are refrigerated and defrosted independently of one another. Individual refrigeration/defrost controls are provided in solid state form for the respective evaporators, and the individual controls are connected with a master control that prevents all of the evaporators from being defrosted at one time. The master control includes a digital time clock providing time signals to each of the individual refrigeration/defrost controls, and each of the individual controls can initiate a defrost operation for its respective evaporator on either a timed or demand basis. The master control includes a scanner that interrogates the individual controls in a special manner to initiate defrosting of the units in order of priority. The master control permits an individual defrost control for a selected evaporator to be tested in a timed mode by substantially increasing the speed of the time clock while operation of the remaining defrost controls is inhibited.

An interface circuit for transmitting and receiving binary data as between a plurality of transmitting/receiving units such as for example electronic typewritters which are connected together. The circuit is suitable for transmitting and receiving data and timing (clock) pulses on two different lines, at a frequency particular to the transmitting unit. The circuit is provided with a binary counter prior to the transmission of data, the clock line is sampled to establish if the line is free and thus ready to receive, or occupied.