The testing apparatus disclosed herein is adapted to test backplane wiring so as to determine if all desired connections exist and whether any undesired connections may be present. Such backplanes typically comprise a multiplicity of terminal points which may be interconnected in arbitrary manner to form a plurality of networks of connected points. The tester employs an addressable switching and memory unit for each terminal point. When addressed, each point is first connected to a first bus and, when the addressing is terminated, is thereafter connected to a second bus, this second connection being maintained under the control of the memory or latch associated with each switching unit. Prior to being addressed, each point is in effect isolated by the switching unit and allowed to float in potential. As the successive points in a given network are addressed, the system tests for continuity between the first and second buses to determine if the desired connections exist. After all terminal points which should be in the selected network have been latched into connection with the second bus, all remaining points are commonly switched into connection with the first bus. Testing for isolation at this time determines whether any undesired connections affecting the selected network are present.
A logic circuit having a test data loading function, comprising at least one J-K flip-flop. Each J-K flip-flop includes a test data latching logic circuit. In response to an enable signal, test data is selected in place of the usual J and K input data to be latched. In a complex logic circuit including such flip-flops, a test can be effected in a short time.
A circuit for the in-service testing of a logic timer generating an internally-preset time-delayed output logic state in response to a timer control input logic state, including a first logic operator having an output equal to the logic product of the negation of the timer control logic input and an enable signal derived from the negation of the timer logic output; a second logic operator having an output which is the timer control logic input and is equal to the logic sum of a master input logic signal plus the output of the first logic operator; and a delay generator having an input which is the timer output logic signal and having an output which delays the return transition of the first logic operator output for a fixed duration of time less than the effective time required for actuation of the timer output load, whereby a master input logic state of duration greater than the time internal delay period produces a timer output logic state which begins at the end of the internal time-delay period and which ends with the cessation of the master input logic signal and a master input logic signal of duration less than the timer internal delay period produces a timer output logic state which begins at the end of the internal time-delay period and has a duration equal to the time-delay period of the delay generator, whereby the timer output load is not effectively activated.
A logic circuit, which includes master-slave flip-flops, advantageously designed to place both the master and the slave flip-flops in a predetermined logic state so that the logic circuit can be tested in one clock cycle in the same manner as a combinational logic circuit is tested.
An integrated circuit having circuitry for clamping input terminals that remain unconnected after assembly into a system. A transistor is connected to clamp the input terminal to reference potential and provide regenerative feedback to a NAND circuit forming a latch which maintains the transistor on when the input terminal would otherwise be left floating. Alternatively, when the terminal is connected to supply potential, the transistor is maintained "off", precluding loss of power.
A complementary MOS input circuit not only transfers input signal swinging between conventional logic levels in a normal mode but also provides a control signal upon application of an input signal swinging outside the normal range of logic levels. This control signal is then available to be used to change selective connections in an integrated circuit to change its operating function, for example. The input circuit includes first and second complementary MOS transistors arranged like an inverter but having their gates connected to a fixed potential and having input signal potential applied to the source of the first transistor. The transistors exhibit an output signal at the interconnection between their drain electrodes which output changes state on an input swinging past the fixed potential sufficiently to render the first transistor conductive.
