While executing program code arranged in nested blocks, a data processing system accumulates words in a stack storage means comprising a pair of registers coupled to an arithmetic unit and supplying thereto operands for processing; a plurality of memory locations in a relatively large-capacity, low-speed memory; and a relatively small-capacity, high-speed memory having a plurality of addressable extension locations. Register means are set to associate the extension locations in one-to-one correspondence with a group of memory locations so as to define corresponding pairs of locations. Each pair is reserved for storing a different stack word and has four occupancy conditions. Before the actual accumulation of the stack word for which the pair is reserved, the pair is in a first condition wherein both locations of the pair are unoccupied. After actual accumulation, the pair is either in a second condition wherein only the extension is occupied, or in a third condition wherein only the memory location is occupied, or in a fourth condition wherein both locations are occupied. Preferably each extension location has occupied and copy indicating storage cells having four states each indicating one of the four possible conditions. Stack words forming the record of execution of a first program block are initially accumulated in the extension locations. When a second program block nested within the first program block is entered the record of execution of the first block is transferred to the presently corresponding memory locations and then the associating register means is set to associate the extension registers with a different group of memory locations so that the extension locations are available to store stack words for the second block. The stack includes a linked list of control words containing stack depth information indicating the number of stack words accumulated in executing each block. Upon a transfer of control from the second block back to the first block the stack depth information is used to set the associating register means so that the required number of extension locations are again reserved for storing the previously accumulated record of execution of the first block. Instead of indiscriminately transferring the record of execution of the first block back to such reserved extension locations, the occupancy and copy indicating storage cells for each such reserved extension location are set to indicate that only the respective memory location is occupied. Thus upon a further transfer of control to another block, the occupancy and copy indicating storage cells provide information used to eliminate unnecessary transfers of words to memory locations already storing the proper words.
A data processing system providing user interaction in multiple natural languages, including a processor for executing application programs and a memory for storing message files corresponding to the application program in at least one natural language and a link table for storing links between the application program and corresponding message files, wherein a link for an application program stores a natural language and a pointer to its message file, wherein the operating system for the processor establishes links when a message file is loaded into memory. The data processing system nests language information for nested application programs. A fall-back mechanism is used to provide a default language when a language desired by a user is not available or when nested languages are not available. The system may send and receive messages in multiple natural languages for multiple users using different application programs simultaneously in a manner transparent to the user and the application programmer with the assistance of the operating system involvement in establishing links, using default languages and nesting language information.
Segments of memory are allocated to a stack cache as needed to accommodate additional continuation frames during execution of a program. When a continuation is captured, flags in all segments of the stack cache are set to indicate the signals are shared by a captured continuation, the top segment of the stack cache is copied, and the copy is made the top continuation frame of the stack cache. To invoke a continuation, the top segment of the invoked continuation is copied into the current stack cache segment. When the stack cache is ready to underflow into a segment shared by a captured continuation, the shared segment is copied and the stack cache underflows into the copy.
An information transferring apparatus comprises a central processing unit, and an input/output unit, a first-in first-out stack having a plurality of memory elements connected in series and being disposed between the central processing unit and the input/output unit, a command register which is set to a predetermined state under program control by the central processing unit, and a control circuit which receives a signal produced from the command register when the command register is set to a predetermined state and applies a signal designating the memory element which is to be the first memory element of the first-in first-out stack from which information is to be transferred and permits the information stored in the first memory element to be read out directly to the input/output unit.
A data memory system includes a plurality of buffer regions each having a constant size so that serial data may be stored by linking the buffer regions. A descripter provided to correspond to each of the buffer regions includes memory region addressing information indicating the head address of the corresponding buffer region, data delimiting information indicating whether or not the data to be stored is terminated in the corresponding buffer region, and chain information indicating the head address of a next subsequent descripter.
A system in which a device or machine is controlled by instructions from a data processor is provided which minimizes main memory storage requirements. An interrupt service routine monitors the input to the processor received from the device in response to control instructions sent by the processor. The interrupt service routine monitors this response for exception conditions. When an exception condition indicating that the device is no longer capable of fully carrying out processor instructions is received by the interrupt service routine, it activates an exception handler routine. A primary memory storage stack normally supports the interrupt service routine. However, upon the activation of the exception handler routine, this primary storage stack is switched to support the exception handler routine, and a secondary stack of significantly lower storage capacity is placed in support of the interrupt service routine which should have lower purported storage requirements during the active period of the exception handler routine. This results in a substantial saving of main processor memory capacity which otherwise would have to be dedicated to the support of the two respective routines.
