An improved memory device to be used in a D.C. curcuit which device includes a pair of spaced electrodes between which extends a body of a generally amorphous high resistance memory semiconductor material made of a composition of at least two elements and wherein the application to the electrodes of one or more set voltage pulses in excess of a given threshold level produces relatively low resistance filamentous path comprising a deposit of at least one of said elements in a crystalline or relatively ordered state. When one or more D.C. current reset pulses of a given value and duration are fed through the filamentous path, the crystalline deposit is returned to a relatively disordered state and the more electropositive element of said composition normally tends to migrate to the negative electrode and the more electronegative element thereof normally tends to migrate to the positive electrode. The improvement is that the amorphous memory semiconductor in the fabrication thereof is provided adjacent substantially the entire surface area thereof facing one of the adjacent electrodes an electrode-memory semiconductor interface region containing a substantially higher concentration of said element which would normally tend to migrate thereto during said reset operation, such electrode-memory semiconductor interface region being sufficiently extensive and having a sufficient concentration of said element to effect a stabilized gradient of said element through the reset region of the semiconductor material in at most a small number of set-reset cycles, so that the threshold voltage stabilization is achieved substantially immediately thereafter.
This disclosure relates to an electrically alterable amorphous memory device which can be switched from a high resistance state to a low resistance state, which device has a stable voltage threshold that is temperature insensitive throughout the lifetime of the device. The memory device is formed of a graded structure having at least three regions or layers of amorphous material selected from the tellurium based chalcogenide class of materials, particularly tellurium-germanium systems. The center or middle region is formed of the eutectic material which is in the range of 15 to 17 percent germanium although this range may vary from 10 to 25 percent. The top region or the region closest to the positive electrode is primarily tellurium with from 0 to 10 percent germanium. The bottom region or region closest to the negative electrode is formed of a material which has the highest glassy state transition temperature which material is approximately 33 percent germanium although this may vary from 25 to 45 percent germanium.
This disclosure relates to an electrically alterable amorphous memory device which can be switched from a high resistance state to a low resistance crystalline state. The device has increases in the concentration of those particular elements at the electrodes to which the respective constituents would migrate during a large number of set-reset cycles. This lessens the decline in the threshold voltage caused by the electromigration of those constituents. There is disclosed a layered structure in which a layer rich in one appropriate constituent is placed between the amorphous memory material layer and the respective electrode and another layer of material rich in the other constituent is placed between the amorphous material and the other electrode. Specifically, there is disclosed a tellurium based chalcogenide as the memory layer. A layer of substantially tellurium is placed between the amorphous memory layer and the positive electrode while the layer of germanium and tellurium in a ratio of approximately 1:1 is placed between the amorphous material and the negative electrode.
Method for the production of devices having a memory action with amorphous semiconductors, comprising in sequence a substrate on which is deposited a lower electrode, an active area produced by means of an amorphous semiconductor compound and an upper electrode, comprising producing the active area in the form of a central layer constituting an active layer formed from a first amorphous semiconductor compound and at least one buffer layer placed on one of the upper and lower faces of the active layer, said buffer layers being formed from a second amorphous semiconductor compound in the form of a quaternary compound selected from the group containing germanium, tellurium, arsenic and sulphur and producing at least one of the electrodes in such a way that it constitutes the actual electrode and with a thin layer turned towards the active area constituting a barrier, wherein the actual electrodes are made from a metal chosen from the group including tungsten and tantalum which can diffuse into the buffer layers and which with the second amorphous semiconductor compound constituting the said buffer layers can form a binary compound with a hexagonal structure in such a way that the barrier necessary for stabilizing the semiconductor is formed.
The Write/Erase lifetimes of amorphous memory devices are extended by applying a multilevel erase pulse wherein the first stage has a current amplitude sufficient to heat the crystal filament to the phase change temperature but not to provide the energy for the phase change and erasure of the crystal structure and the second stage has a current amplitude sufficient to heat the filament to remove the crystal structure. Preferably the first stage current is equal to the write current and the second stage is equal to the write current times the ratio of the electrical conductivity of the amorphous conducting state to the apparent conductivity of the crystalline state.
The Write/Erase lifetime of amorphous memory devices are extended by applying an erase pulse sequence having a first plurality of reset voltage pulses having a maximum amplitude less than the maximum threshold of the device to produce first amplitude current pulses and a second plurality of reset voltage pulses having a maximum amplitude greater than the maximum threshold to produce second amplitude current pulses having an amplitude substantially less than said current pulses. Constant current sources apply the two current pulses when the device threshold is below the maximum voltage amplitude of the first reset voltage pulses and only the second amplitude current pulses when the device threshold exceeds the maximum voltage amplitude of the first reset voltage pulses.
