or
Bookmark and Share
   
Document Number
US Patent 3890600
Issued Date
June 17, 1975
Link
Inventors
Map
Abstract
A method of controlling the entry and removal of characters from a recirculating buffer store is described. The buffer store has a plurality of data storage channels within which the respective bits or elements of a character entered into the store are circulated, and an index bit of the same given polarity is entered into an index storage channel each time a character is entered in the store. The method further comprises recirculating the bits in the index channel in synchronism with the bits in the data channels, sensing the singal level at the output of the final bit location in the index channel, generating a write enable signal to permit the entry of a new character into the store only in response to a transition of the sensed index signal level in a first direction, and generating a read enable signal to permit the removal of a character from the store only in response to an index signal transition in the opposite direction.
Drawing
Buffer stores - US Patent 3890600 Drawing
Drawing from US Patent 3890600
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
4
Comments:
no comments yet
Published
June 17, 1975
Application Number
05/422,514
Filed
December 7, 1973
US Classification
710/53  
Int'l Classification
G06F   5/06   (20060101)   G06F   5/08   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
Dec 11, 1972 [GB] 57074/72
USPTO Field of Search
340/172.5   340/174.1P  
Related Patents
4027292 - Synchronous data processing system having arithmetic and control units controlled by single-phase clock pulses - Owned by Nippon Electric Company, Limited (Tokyo,JA)

A synchronous digital data processing system employing single-phase clock pulses comprises arithmetic and control units which are capable of completing an operation during one clock pulse period. The data processing system includes closed data paths wherein only one stage of a memory circuit capable of the same operation as a master/slave flip-flop is used as a data register in the arithmetic unit and as an address register in the control unit. In either case, during one cycle of a single-phase clock pulse, an input data is set in the memory circuit, and the output of the memory circuit is renewed in response to the input data. The output of the memory circuit is held until it is renewed in the following cycle.

Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us