A system for determining the presence or absence of data on one or more data lines including a flip-flop for each data line with the output of each flip-flop connected to a NAND gate. The NAND gate is connected through an OR gate to two output flip-flops in series. The logic of the system is such that the output of the second of the two output flip-flops provides a signal level which is high or low depending on whether data is present on all of the data lines or one or more lines has no data.

An abnormal signal detecting device, comprising a signal sampling and conversion circuit for sampling a predetermined number of data points along an analog signal and generating digital sampled data signals representative thereof; a memory circuit, connected to the signal sampling and conversion circuit, for storing the digital sampled data; and a consistency detecting circuit, connected to the memory circuit, for comparing at least three consecutive digital sampled data signals and generating an output representing an abnormal condition whenever at least three consecutive digital sampled data signals are the same.

Inherent clock information included in a digital signal of the type in which binary information is represented by signal level transistions which are present on a periodic basis, such as a signal level transistion at a mid-location of a bit interval, is recovered by generating a pulse at each signal level transition, delaying that pulse by a half bit interval and by a full bit interval, respectively, and summing the generated, the half bit delayed and the full bit delayed pulses to recover the clock information. The recovered clock is used to write each binary level included in the received digital signal into a memory from which each stored binary level is read at a reference clock rate. Loss of synchronization between the received and read-out digital signals is detected by sensing a differential of predetermined magnitude in the write-in and read-out rates. Preferably, the detected differential in these rates is used to adjust the read clock rate in a direction which tends to null that differential, thereby restoring synchronism between the read out and written in digital signals.

A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.