In a data processing system employing a virtual storage system, a plurality of address translation pairs each consisting of a logical address in a virtual storage space and a real address in a real storage space, are registered in a buffer storage device to swiftly translate a logical address into the corresponding real address. According to this invention, in the case of purging a virtual space out of multiple virtual spaces only the address translation pairs corresponding to the virtual space are purged so that the processing performance of the data processing system can be improved.

The embodiment relates to special controls in a processor to prevent synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual page addresses in multiple address spaces into real main storage page frame addresses. The controls use a synonym resolution register (SRR) which divides each address space in the system into common and private portions. Fields in the SRR indicate which portions are to be common to all address spaces, and which portions are private in each address space. A SRR control circuit selects a particular status field under control of a virtual address requesting main storage access. Each DLAT entry contains a common/private storage indicator which is controlled by the particular status field when the DLAT entry is loaded. When the DLAT entry is read, the private/common storage indicator controls whether the DLAT entry can only be used privately by the address space identified in the DLAT, or commonly by all address spaces.

An address conversion system comprises an improved associative memory circuit for providing a real address corresponding to an applied virtual address with reference to the correspondence between virtual and real addresses stored in a main memory. The associative memory includes first and second memories for storing a part of the correspondence between virtual and real addresses. The second memory is essentially a set associative memory but is not connected with address comparators directly. The first memory is higher in speed but smaller in capacity than the second memory. When the first memory stores the correspondence between the virtual and real address corresponding to the applied virtual address, the real address corresponding to the applied virtual address is immediately delivered.

An arrangement for dynamically translating virtual address into absolute or physical addresses of items of data. Each virtual address includes a segment table number, a segment table entry, and a segment page number. Segment descriptors are stored in a central memory. The address of a particular segment descriptor may be calculated from the segment table number and the segment table entry. From the segment descriptor, a unique identification termed a logic page number may be calculated. The logic page number permits pseudo-associative access to a table containing a number of entries proportional to the number of physical pages of the main memory, allowing the physical address to be determined.

The embodiments relate to special controls in a processor which eliminate synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual addresses in multiple address spaces into real main storage addresses. The controls provide a common space bit in any segment table entry (STE) or alternatively in any page table entry (PTE) in any private address space to indicate whether the segment or page, respectively, contains programs and data private to the address space or shared by all address spaces. Each DLAT entry contains a common/private storage indictor which is set to the state of the common space bit in the STE or PTE used in an address translation loaded into the DLAT entry. When the entry is read, the private/common storage indicator controls whether the DLAT can only be used by the address space identified in the DLAT, or by all address spaces.