In a data processing system including an associative store for rapid translation of recently used virtual page addresses to corresponding real page addresses to access main store, an additional storage means is provided to hold data representative of a boundary in main store below which translation is not required, i.e. the virtual address is used to access this lower part of main store. This lower part of main store is often referred to as the "nucleus"; and selected parts of the "operating system" and selected data are held in this area during normal machine operation. The additional storage means significantly improves system performance with a minimum increment in cost by minimizing the amount of loading and unloading of the associative translation storage means. High frequency of use instructions and data are preferably assigned the virtual addresses below said boundary.
An address conversion system comprises an improved associative memory circuit for providing a real address corresponding to an applied virtual address with reference to the correspondence between virtual and real addresses stored in a main memory. The associative memory includes first and second memories for storing a part of the correspondence between virtual and real addresses. The second memory is essentially a set associative memory but is not connected with address comparators directly. The first memory is higher in speed but smaller in capacity than the second memory. When the first memory stores the correspondence between the virtual and real address corresponding to the applied virtual address, the real address corresponding to the applied virtual address is immediately delivered.
A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.
Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated. If the two compare then the real address which had been used to access the page directory is entered into a register so as to be available as a real main storage address. In actuality it is only a partial real main storage address and is concantenated with a byte identifier portion of the main storage address which requires no translation and which was a part of the original I/O real address for main storage.
An address converter for converting logical addresses of a program to physical addresses of a memory device comprises a first address converter having entries corresponding to the logical addresses of the program on a 1 : 1 basis. The first address converter stores physical addresses corresponding to the logical addresses. Each entry of the first address converter has data indicating whether or not the memory area of the memory device corresponding to physical addresses stored in such entry is commonly used for applications. A second address converter has unique entries, each commonly selected by any of the logical addresses corresponding to each memory area of the memory device commonly used. The second address converter stores physical addresses corresponding to the memory areas of the memory device commonly used. The entry of the second address converter is indexed by a physical address stored in an entry of the first address converter, which entry of the first address converter includes data indicating that the corresponding memory area is commonly used.
A memory space for storing computer instructions includes first and second groups of addresses for first and second types of computer instructions. The first and second groups of addresses are numbers in first and second bases, respectively. The memory space is addressed with signals representing numbers only in the second base. All of the addresses of the first base are expressed by numbers that form only some of the numbers of the second base. In response to an indication of the first type of computer instruction being read out of or into the memory, the addresses of the first base are converted into addresses of the second base.
