Herein is disclosed a circuit adapted for determining whether or not the number of corresponding bits in two parallel arrays of binary signals, which are of the same binary state, exceeds a preselected number. In accordance with one embodiment of the invention, a parallel array of cascode logic circuits is employed wherein each cascode circuit provides differential currents which are indicative of whether or not two applied bits, one from each signal array, are of the same binary state. Differential output currents from a programmable current source are summed with the differential currents from the cascode circuits and the resultant sum signal is applied to a comparator circuit whose output signal is indicative of whether the degree of correspondence between the two arrays exceeds a level determined by the programmable current source.
A digital m of n correlation device using signal and reference shaft registers, modulo 2 adders, unique 1-bit D/A converters, and single resistor analog summing provides a very fast correlation product for pulse compression modulations such as phase or frequency shift keying. The compression ratio for the digital m of n correlation device, according to the present invention, is 168:1 (equal to the number of bits). The device is capable of bit rates in excess of 100 Mbps and is well suited for LSI fabrication.
An apparatus for post-correlation signal processing includes a plurality of correlators for correlating a received signal with a predetermined signal to produce a plurality of correlator output signals and a selection circuit coupled to the plurality of correlators for selecting a correlator output signal from one of the plurality of correlator output signals to provide a selected correlator output signal. A memory is coupled to the selection circuit for storing post correlation totals. A counter is coupled to the memory for synchronizing the memory with the predetermined signal. An adder is coupled to the memory and to the selection circuit for combining the selected correlator output signal with the post correlation total from the memory to form a new post correlation total. The memory replaces the previous post correlation total with the new post correlation total.
A digital complex correlator for correlating in-phase and quadrature components of data samples by shearing the in-phase and quadrature data pairs by a predetermined multiple of the noise in the correlation window under analysis. The sheared data is multiplied by a variable factor generated in accordance with the shearing threshold and the number of samples in the window. The variable factor is generated to maximize the precision in the data while avoiding overflows in the complex multiplication and accumulation of the correlation process.
A design for a differential amplifier with a large input common mode signal range. The differential amplifier comprises two differential pairs, each having two amplifying MOSFETs. A source follower is connected to the gate terminal of each amplifying MOSFET in one of the differential pairs. A differential signal applied to the differential amplifier comprises two separate signal. Each separate signal is applied to the gate terminals of both the amplifying MOSFET in the differential pair not driven by the source follower and the driven MOSFET of the source follower. The differential amplifier further comprises a pair of switch MOSFETs connected to a current source MOSFET. The switch MOSFETs act to control the distribution of the total current flowing from the current source MOSFET and, consequently, to determine which differential pair works dominantly to amplify the input signals. Each source follower acts to offset the voltage of its input signal to compensate for the range loss due to the bias voltages and the threshold voltages within the differential amplifier.
An improved digital parallel correlator is disclosed. Illustratively, the inventive correlator utilizes a shift register which receives a signal comprising data bits encoded as chips. At each cycle of the signal, the chips in the shift register are compared to a reference sequence and the number of matches is obtained. Whenever the number of matches exceeds a fixed high threshold or falls below a fixed low threshold, indicating the presence of a binary 1 or binary 0 data bit, the chips in the shift register are set to a predetermined sequence such as the reference sequence or its complement. This amounts to correcting any chips of a bit that are received in error as soon as it is determined that the bit is a binary 1 or binary 0. This enables the high and low thresholds to be located as far as possible from the peak correlation values thereby increasing the number of chips that can be received in error.
