An integrated circuit memory system includes capacitive storage memory cells capable of storing n bits of information on n capacitors associated with multiple emitters of a bilaterally conductive bipolar transistor. Each capacitor is coupled to a separate bit/sense line. Access of a storage cell is achieved by forward biasing the common base/collector junction of the bipolar transistor. Writing is achieved by driving the bit/sense lines to charge or discharge the storage capacitors during an access cycle. In reading, or sensing, the charged state of each storage capacitor is determined by sensing potential changes on the bit/sense lines during access. Fabrication of memory arrays is possible by any one of several different techniques, all of which are compatible with high speed bipolar logic circuits.

A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

A negative resistance device formed by series-connection of a complementary pair of insulated gate type FETs (field effect transistors), the source of the FETs being connected to each other and the gates of each of the FETs being connected to the respective drain of the other FET at least one FET having a double layered gate insulation film under the gate electrode, thereby forming a non-volatile memory element. The negative resistance device acquires or loses negative resistance characteristics by responding to signals to the gates, thereby memorizing the signals and resulting in a highly efficient memory which requires little power in writing-in, erasing and memory-holding.

JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.

A semiconductor charge storage and detection device is provided in which an ion implanted conductive channel is buried between source and drain regions in the bulk of a semiconductor substrate. A charge storage region extends between the channel and the surface of the semiconductor device. The charge storage region is isolated from the semiconductor substrate and may be depleted of charge or enabled to store charge depending upon the electrical potential applied to a gate electrode at the surface of the device. The amount of charge stored may be detected by sensing the conductance of the buried channel. The device may be variously configured, e.g. as a non-destructive readable photosensor or as a memory cell.