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Frequency discrimination circuit
   
Document Number
US Patent 3906382
Issued Date
September 16, 1975
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Abstract
A signal to be discriminated of frequency f.sub.1 and a reference signal of frequency f.sub.2 are applied to a mixer which outputs two quadrature phase related, reversible beat frequency signals e.sub.a and e.sub.b, in accordance with the frequency conditions of f.sub.1 < f.sub.2 or f.sub.1 > f.sub.2. The signals e.sub.a and e.sub.b are coded into two level signals as to their respective levels. A phase discrimination circuit receives the signals e.sub.a and e.sub.b and outputs an AC signal at the beat frequency, selectively at one or the other of its two output terminals in accordance with a leading or lagging (delayed) phase relation of one beat frequency signal relative to the other, the phase of which is taken as a reference. The phase discrimination circuit includes a memory circuit which stores the condition of the levels of the level coded signals e.sub.a and e.sub.b occurring during a predetermined one-fourth period of a cycle and produces a corresponding output. Means then respond to the memory output and at least one of the beat frequency signals to produce an output indicative of the leading or lagging phase relation of one beat frequency signal relative to the other.
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Frequency discrimination circuit - US Patent 3906382 Drawing
Drawing from US Patent 3906382
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Number of Claims:
16
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Owner
Fujitsu Ltd. (Kawasaki,JA)
Published
September 16, 1975
Application Number
05/495,299
Filed
August 6, 1974
US Classification
327/42   327/3
Int'l Classification
H03D   13/00   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Aug 09, 1973 [JA] 48-89432
USPTO Field of Search
328/133   328/134   307/233  
Related Patents
5053651 - Deglitched digital mixer circuit - Owned by Rockwell International Corporation (El Segundo, CA)

A digital mixer employs a plurality of flip-flops to mix two digital input signals and provide a beat frequency output. The first input signal is provided as a clock signal to a first D flip-flop and to a third JK flip-flop. The second input signal is provided as a clock signal to a second D flip-flop. The inverted output of the first flip-flop is provided as a clock input to a fourth JK flip-flop. The non-inverted and inverted outputs of the second flip-flop are connected, respectively, to the J and K inputs of the third flip-flop. The non-inverted outputs of the second and third flip-flops are input to a first AND gate, the output of which connects to the J input of the fourth flip-flop. Likewise, the inverted outputs of the second and third flip-flops are input to a second AND gate, the output of which connects to the K input of the fourth flip-flop. The non-inverted output of the fourth flip-flop provides a beat frequency that is one-half the difference frequency of the two input signals. The third flip-flop in the digital mixer prevents glitches around the transition time of the beat frequency output even for very low beat frequencies.

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Description
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