A CCD memory device having on a single chip a parallel multi-channel storage section into which data is fed by a serial input register and from which data is read by a serial output register. Although at least two storage electrodes are needed throughout the memory to store each bit of information, the total number of such electrodes required in the input and output registers is greatly reduced by alternately storing the input and output bits at even and odd numbered storage electrodes of the input and output registers, so that each storage electrode may serve a separate channel of the parallel storage section.
A bidirectional serial-parallel-serial charge-coupled device wherein each serial section is both an input register and an output register, and serial streams of charge packets flow simultaneously in opposite directions in the parallel section. Odd data bits of a serial input stream flow into a first serial register and then through the parallel section in one direction and then out of the second serial register, while concurrently the even data bits flow into the second serial register and then through the parallel section in the opposite direction and then out of the first serial register. The data transfer rate is thereby substantially doubled.
The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit. The input and output sections each contain (almost) twice the number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site. Data bits are transferred into and out of the central section in one parallel step, thereby minimizing the clocking requirements of the register and allowing for high density CCD chips containing such registers.
The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two-phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit. The input and output sections each contain the same number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site. Data bits are transferred from the input section to the central section in two phases. Data bits are also transferred from the central section to the output section in two phases. This interleaved mode of inter-sectional data transfer allows for input and output sections of a minimum size (in terms of number of cell sites required) and hence, a greater density CCD register. The interleaved mode also reduces the number of charge transfer from input to output, thereby providing inherent charge transfer efficiency.
In the present invention, image processing is performed at speeds comparable to those achieved in parallel processing without requiring substantially more area on the substrate than that required in serial processing. In this invention, for an N.times.N processing kernel, N rows of image memory are processed in parallel through a plurality of N floating gate arrays of dimension N.times.N, N-1 of the data rows from the memory being recirculated through the N floating gate structures before being discarded. Each of the floating gate structures is offset from the adjacent floating gate structure by one row so that the data from memory need be recirculated only once.
The area of an integrated delay line comprising charge transfer circuits (charge-coupled circuits and bucket brigade circuits) is minimized by arranging the stages in such a manner that between two longitudinal chains of stages there lie n/2 transversal chains, n being the number of stages of one longitudinal chain.
