An internal correction circuit is provided to correct the timepiece error caused by the crystal oscillator frequency changes. The timepiece operates by frequency dividing the oscillator frequency to obtain a predetermined operating frequency. The correction circuit is operated by the user on any initialization point, such as the start of any minute from a reference time source to generate a first input signal. The user at any following minute of the reference time source generates a second input signal. The correction circuit counts a first and second number of time units of different lengths between the first and second input signals. The circuit then forms a division ratio from the first and second numbers. That ratio is used to change the frequency divider division ratio to adjust the watch for the crystal frequency error just calculated.

An electronic timepiece including a variable divider for producing timekeeping signals for the smallest digit of time displayed having a frequency which is not evenly divisible into the frequency produced by the time standard. An oscillator includes a time standard for producing a high frequency time standard signal having a frequency of K.sup.N Hz where K and N are positive integers other than O, and a divider adapted to evenly divide the high frequency time standard signal by K.sup.M, where M is an integer other than O, and in response thereto produce a K.sup.N.sup.-M frequency signal having a frequency not evenly divisible by I.sup.P, where I is a positive integer other than K and P is an integer. A counter is provided for producing output signals representative of a counting cycle in response to an input pulse signal applied thereto, and a display device is coupled to the counter for displaying each count of the cycle thereof. A detecting circuit is coupled to the counter to detect at least one predetermined count of each counting cycle thereof, and in response to each predetermined count produces a detection pulse. The variable divider is coupled to the detection circuit and has a first and second division ratio. The variable divider is adapted to receive the K.sup.N.sup.-M frequency signal and in response thereto divides same by a first division ratio, and in response to each said detection pulse applied thereto divides the K.sup.N.sup.-M frequency pulse by said second division ratio to thereby produce an input pulse signal to the counter having a frequency evenly divisible by I.sup.P.

A frequency generator comprises a quartz crystal controlled oscillator subjected to at least one variable physical parameter such as temperature and has an arrangement for calibrating the frequency with respect to a standard signal with simultaneous compensation for variations of the physical parameter(s). This arrangement comprises a first set of selectable memories storing values to control the division ratio in a dividing chain. These memories are inscribed in a learning period for a few values of the physical parameter(s); simultaneously, digital values supplied by at least one probe, each value corresponding to a range of values of the parameter, are stored in a second set of memories associated with the probe(s). During operation of the generator, a comparator compares the actual digital value supplied by the probe(s) with the values stored in the second set of memories, to select the corresponding memory of the first set for controlling the division ratio, at least one probe sensitive to a physical parameter of the environment, and means associated with each said probe to form selection signals each selection signal representing various possible values of the parameter considered in one of several ranges of values of said parameter, said electrically-alterable memory being arranged in groups to be selected by said selection signals and each corresponding to one of said ranges to memorize values determining the division ratio to be adopted as a function of said signals, the generator further comprising calibration selecting means for connecting the output of the frequency comparator to the inscription input of the selected memory group.

An electronic timepiece having circuitry for automatically adjusting the time rate by comparing same to a randomly selected reference, is provided. A timing rate circuit includes an oscillator for producing a high frequency time standard signal and a divider for producing a low frequency timekeeping signal. The divider includes a plurality of series-connected divider stages, each divider stage being adapted to produce an intermediate frequency signal. A counter is provided for receiving the low frequency timekeeping signal and producing an elapsed time signal representative of time counted thereby. The instant invention is particularly characterized by an error counter coupled to one of the divider stages for receiving an intermediate frequency signal produced thereby for a randomly selected reference period. A reference counter is coupled to the counter in order to receive one of the elapsed time signals produced thereby for the randomly selected reference period and in response thereto is adapted to produce a reference count signal. A processing circuit is adapted to compare the error signal and reference count signal and in response thereto is adapted to apply a frequency adjusting signal to the timing rate circuit to regulate the timing rate of the low frequency timekeeping signal produced by the divider.

An electronic timepiece apparatus which comprises an electronic time-counting circuit including an oscillator generating standard clock pulses; time-setting means including an actuating switch for correcting the value of a count made by the electronic time-counting circuit; means for correcting the value of a count made by the electronic time-counting circuit for each prescribed period in accordance with the amount and direction of correction determined as the result of comparison by the time-setting circuit between a given point of time and the correct time; and display means for indicating a given point of time just counted by the electronic time-counting circuit.