A rapid response current limiter is used in combination with first and second switching transistors and an output transformer winding connected to provide a power converter. The transistors are alternately switched by first and second square waves supplied to their base terminals, an input d.c. source being connected between a common junction of the switching transistors and a center tap of the transformer winding. Rapid response current limiting is accomplished by limiting the width of the driving square waves applied to the transistors to thereby limit the peak current that they conduct. This limiting of square wave width is accomplished by gating circuits which abruptly truncate the square wave causing the switching transistors to turn off whenever a sensed current in the circuit exceeds a given reference value. The current limiting acts virtually instantaneously so that the risk of burning out the switching transistors in the event of a sudden high current surge is substantially eliminated.
A switched mode power supply employs a pulse width modulation controlled DC-to-DC converter to change a first voltage from a source of DC power into a regulated power source providing direct current at a second DC voltage. A transformerless current-sensing device is adapted for connection in the path between said source and said converter and provides a control signal which is representative of the current flowing in said path. A current-limiter control circuit is responsive to said control signal and provides an enabling output state when the sensed-current exceeds a predetermined value. The enabling state overrides the pulse width modulator control and inhibits the converter, thus terminating the output pulse when the sensed current exceeds said predetermined value.
Disclosed is an overcurrent protection apparatus in a switching power supply, including a power switching element for interrupting the primary current of a transformer, and a control circuit for generating control pulses which are modulated in pulse width in accordance with a variation in the rectified output voltage on the secondary side of the transformer, the opening and closing of the power switching element being controlled by the control pulses to maintain the rectified output voltage at a constant value. The overcurrent protection apparatus further includes overcurrent detection means which issues an overcurrent detection signal after detecting that a current flowing into the power switching element has exceeded a prescribed value; memory means set by the overcurrent signal; a gate circuit for blocking the passage of control pulses when the memory means has been set; and reset means for resetting the memory means in response to the trailing edge of a control pulse. The switching of the power switching element is controlled by the memory means so that the power switching element is turned off when the memory means has been set, and turned on when the memory means has been reset.
A circuit employing a transformer secondary winding having a fraction of its turns tapped across the base-emitter junction of a power transistor. A silicon controlled rectifier is connected from the transistor base across the entire secondary winding providing control of the power transistor conduction and reverse base drive upon power transistor turn-off. Synchronous control signals for the controlled rectifier may be developed by an additional secondary winding wrapped on the same core as the secondary winding driving the power transistor.
A self-balancing d-c/a-c converter comprises a transformer whose primary winding is split into a pair of symmetrical halves each connected in series with a respective transistor and an associated resistor across a supply of direct current. A differential amplifier, with inputs connected across the two resistors through a pair of low-pass filters, generates an unbalance signal d in the form of a voltage of either polarity which is additively and subtractively superimposed upon a reference voltage e to provide two control signals e+d and e-d fed to respective inputs of two comparators. Two synchronized signal generators produce a sawtooth oscillation a and a square wave f, the latter having a period which is twice that of the former. Sawtooth wave a is fed in parallel to the other inputs of the two comparators while the square wave f and its complement g alternately unblock a pair of AND gates in cascade with these comparators. Two resulting pulse trains h and i, of a pulse width varying with the sign and magnitude of the unbalance signal d, energize the bases of the two transistors in a manner tending to rebalance the current traversing the transformer primary.
An essentially non-dissipative, strap-free, continuously adjustable power unit inherently impervious to shorts and open circuits for powering repeaters in a T1 or similar telephone span line is disclosed. The unit uses a pulse-width modulated inverter in the converter input circuit to produce a variable-voltage D.C. output to the span line. The pulse width or duty cycle of the inverter is controlled by a control logic which senses the span line current and maintains it at a selectable predetermined level without any apreciable power dissipation.
