Disclosed is an electronic calculator system implemented on at least one semiconductor chip having a first set of data storage memory registers for storing a first plurality of multi-digit, multi-bit data words, and further having another storage memory register coupled to the first set of storage registers for storing another multi-digit, multi-bit data word. The said another storage means has an input which is responsive only to one of the first set, under control of an instruction word provided by a permanent store memory. The system further provides an N input arithmetic means coupled to the N data storage means such that (including the said another register) there are N + 1 storage registers providing inputs to the N input adder. By providing the exchange register having inputs and outputs coupled to only one of the first set, input and output select circuitry is eliminated to effect increased packing density.
An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having an arithmetic unit, a memory register and a dual speed shift register, the dual speed shift register being responsive to control signals generated on the chip for controlling the memory register to selectively read out a first or second number of digits of data stored therein to an input of the arithmetic unit.
An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable by the address register, and instruction word decoder logic for decoding the instruction words and for controlling the arithmetic unit in response thereto. The system further preferably includes a plurality of operational registers for storing numeric data received from the input or outputted by the arithmetic unit and a plurality of operational register selector gates coupling the operational registers with the arithmetic unit or with each other. The instruction word decoder logic includes mask logic for generating mask signals to the plurality of operational register selector gates. Thus the instruction word decoder logic decodes instructions for operating selected ones of the plurality of operational registers to effect arithmetic operations by coupling selected operational registers to the arithmetic unit or data exchange operations by coupling selected operational registers together. The mask logic also controls the selected operational registers for determining what portions of the words of numeric data stored in the operational registers are to be operated on arithmetically by the arithmetic unit or to be exchanged during data exchange operations.
An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a arithmetic unit and memory system. The arithmetic unit and memory system include a plurality of operational registers and an arithmetic unit having two inputs and an output. A plurality of operational registers selector gates interconnect the operational registers and arithmetic unit for connecting any selected two of the plurality of operational registers to the inputs of the arithmetic unit. The plurality of operation register selector gates preferably comprise individual MOS transfer gates.
An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having an arithmetic unit for performing arithmetic operations on the numeric data received from the input, a memory for storing a number of instruction words addressable in response to said function commands, an instruction word decoder for decoding instruction words and for controlling the arithmetic unit in response thereto, first and second operational memories for storing numeric data received by said input or outputted from said arithmetic unit and a display system for displaying numeric data stored in a first one of the operational registers according to display codes stored in a second one of said operational registers, the display codes being indicative of which character positions in the display are to be blanked or to be provided with signals actuating a decimal point thereat.
