Clocking apparatus for complex and extensive data processing systems in which the functional logic circuit units are each provided with individual clocking circuits and the several clocking circuits are activated by a central control unit. Operation of the individual clock circuits is initiated by control unit signals and each clock circuit operates at an independent rate. The clocking system is readily adaptable to computer systems using large scale integration (LSI) since the clock circuits can be made a portion of each LSI chip and operated to control the functional logic circuits on that chip. At the conclusion of a functional cycle, a completion signal is transmitted to the central control unit which can then generate additional clock initiation signals as required. The clock circuits also include additional delay circuits which can be activated to add predetermined amounts of delay between selected clock output signals to permit remotely adapting the clock timing control to the requirements of a functional logic unit.
A master clock for a microprogrammed digital computer generates output pulses whose separation in time can be varied in response to each microinstruction or to a process-related signal. The output pulses are formed from basic time units from a clock generator which are combined, in digital logic circuitry, to form a minimum time interval and supplemented, under command, with the necessary additional time units to delay the next output pulse by the required amount of time.
A mechanism for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. A method and mechanism for indicating to the functional unit whether it is required for use. Also included is a method and mechanism for powering down the functional unit transparent and independent of the rest of the functional units when the functional unit is not required for use.
A system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition instruction; and a clock generator supplied with the output of an oscillator for developing a basic clock of a desired waveform for supply to the system, wherein the basic clock is developed or inhibited when the control signal is supplied from the clock control signal generator.
A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. In the digital system, data transfers on the common bidirectional data bus are accomplished without the use of a memory synchronization signal so that a special signal conductor indicating when the memory is ready to transfer data is not required. This is accomplished by logic circuitry which expands a clock signal pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily applied to the microprocessor to effect its operation.
A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode. Log out data is supplied to the clock distribution circuit from the sequential logic circuit in the log out mode via a specific bidirectional line in accordance with the sequential logic circuit selection signal.
