A feedback circuit between the output and input terminals of a complementary-symmetry, metal-oxide-semiconductor (CMOS) circuit, such as an inverter circuit, quiescently biases the circuit at a point on its transfer characteristic such that a slight additional change in voltage level will cause the circuit to change state. Input signal is applied to the input terminal through a coupling element such as a capacitor. When this input signal starts to decrease after reaching its peak voltage value in a given sense, it causes the feedback circuit to open and the CMOS circuit to change to its second state. In response to each following peak of the same sense, the feedback loop momentarily closes then opens and concurrently the circuit momentarily reverts to its initial state then switches to its second state.
The present invention relates to a CMOS peak detection circuit (10) which does not require a blocking diode as is used in conventional peak detection circuits. The detection circuit of the present invention comprises a comparator which functions to compare the current value of an AC input signal to a current peak value stored on a capacitor (16). The output of the comparator is connected to a NAND gate which in turn activates a CMOS transmission gate (12) disposed between the input signal line and the storage capacitor. When the current value of the input signal is greater than the current peak value stored on the capacitor, the CMOS transmission gate is turned on and the AC input signal is transferred to the storage capacitor. Alternatively, if the current value of the input signal is less than that stored on the capacitor, the NAND gate will not activate the CMOS transmission gate, and the input signal cannot pass to the capacitor. A negative peak detector can be formed merely by inverting the inputs to the comparator and resetting the storage capacitor to the positive power supply instead of the negative power supply. A tandem arrangement of a positive peak detector and a negative peak detector formed in accordance with the present invention may be utilized to determine the DC level of an AC input signal, since each detector will generate the peak positive and negative values of the input signal and the DC level is defined as the average value of these two peak values.
A voltage level shift system transitions a voltage signal between two components and includes a first inverter, a signal pass subsystem, a pull-up transistor, a second inverter, and a third inverter. The first inverter is coupled to the signal pass subsystem. The signal pass subsystem is coupled to the pull-up transistor, the second inverter, and the third inverter. The signal pass subsystem includes a first passgate and a second passgate. When an input voltage transitions from a logic low to a logic high, the first inverter inverts the logic high input signal to a logic low and passes this signal through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a low logic to a logic high. The logic high output signal, turns off the pull-up transistor. When the input signal transitions from a logic high to a logic low, the first inverter receives the signal and generates a logic low signal that passes through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a logic high to a logic low. The logic low signal places the pull-up transistor in an on state to turn off the p-device in the circuit. A method for transitioning a voltage signal between two components is also disclosed.
A pulse generator comprises a CMOS inverter, a capacitive device and a resistive device, where the CMOS inverter has two terminals connected to a source voltage and a reference voltage, e.g., ground, respectively, the capacitor device and the resistive device are connected to the input end of CMOS inverter, and pulses are generated at the output end of the CMOS inverter. The capacitive device is charged by a boost signal and discharged through the resistive device, so as to manipulate a potential at the input end of the CMOS inverter to control the operations of the transistors included in the CMOS inverter, thereby changing the level of the output voltage of the CMOS inverter. The widths of the pulses can be adjustable by a control signal received by the resistive device.
An inverting amplifier is provided with a high impedance input resistor connected at one end to an input terminal of the amplifier and connected at the other end to a first voltage source constituting a first binary logic level. The input terminal is also connected through a switch to a second voltage source constituting a second and opposite binary level. An MOS-FET has source and drain electrodes connected to the input terminal and the first voltage source respectively and a gate electrode connected to an output terminal of the amplifier. When the switch is closed, the second voltage is applied to the input terminal and the inverted output of the amplifier turns off the MOS-FET. When the switch is open, the first voltage is applied to the input terminal through the resistor and the inverted output of the amplifier turns on the MOS-FET. The low impedance of the MOS-FET in the turned on condition increases the stability of the amplifier under high humidity conditions.
A semiconductor device has a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; an interconnection layer, containing an impurity of a second conductivity type, for connecting the first and second semiconductor regions; and a third semiconductor region of the second conductivity type which is formed in the first semiconductor region upon diffusion of the impurity from the interconnection layer to the first semiconductor region, the first and third semiconductor regions being adapted to form a p-n junction diode.
