Memory system employed in a time compression scanner for monitoring telephone lines. Digital samples are written into the storage locations of a memory during one memory addressing period, and these samples are read out during the next memory addressing period, but in a different order from the order in which they were entered. As each sample is read out, it is replaced by a new sample which is to be read out during the subsequent memory addressing period. The memory address for writing in and reading out each sample is controlled by a series of flip-flops. Clock pulses are directed to a different one of the flip-flops during each memory addressing period in a recurring sequence of addressing periods in order to cause the storage locations to be addressed in a different order during each memory addressing period.
A system in which a plurality of analog information sources appearing on a plurality of multiplexer channels are selectively scanned under control of a read only memory. The analog information is converted to digital information having a word length also determined by the read only memory and put in a serial stream of digital information prior to transmission.
A signal processing system includes means for performing a logic function on a multi-dimensional array of information stored in a memory. Typically, the memory stores two-dimensional video information (pixels), and the logic function is a discrete cosine transform (DCT), or other linear operation. The logic function is performed on both rows and columns of the information. In the prior art, this has required two memory spaces, so that information could be written into one memory while being read out of another memory. In the present invention, a single memory space is used to transpose the information between row and column format, by performing a read-modify-write operation on each memory location in a specified sequence.
An apparatus and method are disclosed which find particular utility as a component of a traffic control system known as a conflict monitor. The apparatus includes a number of solid state switches which are activated to scan inputs from traffic control signals. The inputs are sequentially applied to a A-D converter which samples the voltage and applies it to a microprocessor which is programmed to determine the voltage and analyze the signals for conflicts, or other errors. The input lines are also connected to terminals of a program board whereby the microprocessor can instruct a switch to ground the common pin on the program board to allow program board inputs to be applied to the microprocessor for indicating permissible conflicts. A method includes a technique for determining the voltage of an input analog signal by scanning a plurality of input signals and sampling them in accordance with a relationship which provides minimum error. A display may be operated in one of two modes. In the first mode, a display indicates the signals involved in a conflict, or other error determination. In a second mode, the display may be sequentially stepped through each signal to determine its particular state at the time of a conflict.
The device and method disclosed relate to the field of electronic devices and methods enabling the transposition of any even-order square matrix, the elements of which are given in sequence. The goal is to provide for the transposition of sequences of data representing elementary image blocks, without any duplication of the memory space needed to store an elementary block, in optimizing the two parameters of operating speed and space occupied on silicon. This goal is achieved by a buffer memory divided into two identical storage half-planes, working together with a device for the sequencing of the reading/writing operations, providing simultaneously for a reading operation on one of the storage half-planes and a writing operation on the other half-plane.
Sample and hold circuits are utilized to divide data stored in memory into a plurality of channels for display. First-in-first-out buffers are utilized to compensate for the difference between the time required to read data from a memory and the time required for a sample and hold circuit to sample and hold the data.
