Monolithic structures having high circuit density wherein the circuitry is arranged, and/or includes circuitry, to facilitate testing of said monolithic structure. Method for effectively and efficiently testing the circuits arranged and adapted for testing on a monolithic structure having high density. Namely, a test method for testing logic chips and logic chips adapted to be tested by said test method. A test method is disclosed wherein the logic chip, or monolithic structure, is arranged, or divided, into functional sub-assemblies, or logic locks, exhibiting a high degree of testability and includes integrated decoding means allowing individual sub-assemblies to be selected. The decoding means further allow a test pattern applied thereto to be transferred to the selected sub-assembly. Transfer means are provided between the sub-assemblies so as to isolate them electrically from one another during the test operations. The output pattern provided by a sub-assembly in response to the input test pattern applied thereto is applied to gating means which allow all output patterns to be fed to a single output pin. The above abstract is not to be taken either as a complete exposition or as a limitation of the present invention, the full nature and extent of the invention being discernible only by reference to and from the entire disclosure.
The present disclosure describes a device for checking the dc characteristics of electronic nets disposed for example in assemblies utilized in data processing equipment. The operation of the analyzer assumes the presence of one or more controlled impedance nets, as may be achieved through the use of current mode logic configurations. The device which is employed while the circuit under test is in a power-off condition, first determines which type of net is being tested, passes a current of known magnitude through the net, and then compares the actual voltage developed thereacross with expected voltage values falling within a tolerance range. The voltage corresponding to the nominal impedance of the net and the tester current passed therethrough, lies at the center of the range. The analyzer automatically checks all the pins of a monolithic integrated circuit chip in sequence. If the nets associated with all the pins fall within the tolerance ranges, a "good" indication occurs upon test completion. On the other hand, if an out-of-tolerance net is encountered, the testing sequence is interrupted, an error indication is produced, and the pin associated with the "bad" net is identified by the analyzer.
A chip testing system using an internal signal of the chip under test to produce a blanking signal so as to avoid a conflict in the turn-around cycle between input mode and output mode. The preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test are used to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.
The logical circuit includes therein a logic block for performing a logical function. The logic block is connected with the selection circuit and the selection circuit selects the input signals thereto in response to the selection signal. The input terminals of the logic block are connected with a bypass circuit and the bypass circuit transmits the input signals applied to the input terminals of the logic block to the selection circuit. When the selection signal takes the selected one of the values, the input signals to the logic block are bypassed through the bypass circuit, without being passed through the logic circuit, and delivered as the outputs of the selection circuit.
A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode. Log out data is supplied to the clock distribution circuit from the sequential logic circuit in the log out mode via a specific bidirectional line in accordance with the sequential logic circuit selection signal.
A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip.
