A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.

A high speed memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting the columns, a shift register arranged in parallel with the column decoder, and control means for operatively enabling the shift register, in which consecutive access to a plurality of memory cells belonging to the same selected row can be performed from the column address designated by the column decoder.

A semiconductor memory device, comprising N memory cell arrays each of which includes a plurality of memory cells, is arranged to enable the use of said semiconductor memory device in the form of both one-bit-per-word N-bits-per-word. Two separate sets of output gates are provided, together with an additional input line for selecting between the two sets of gates. One set of gates is connected to provide one-bit output, and the other set of gates is connected to provide N-bit output.

In an LSI memory of the invention, in order to decrease the number of input address lines, an address counter having a bit length corresponding to some input address lines is incorporated in the LSI memory to compensate for the number of omitted input address lines. The address counter is counted up in response to a clock pulse supplied through an additional clock input signal line and is initialized in response to a chip enable signal.

A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.