In a logic cell, a plurality of gates are serially connected and responsive to signals on a plurality of conductors to perform a particular logic function. The gates are responsive to subsystem clock signals which control the operation of the gates to delay the output of the logic cell. The cell includes at least one ratioless gate, and at least one ratioed gate. The ratioless gates provide high speed and reduced size, while the ratioed gates provide low noise characteristics. In combination, the ratioed gates, which provide strong output signals, make excellent drivers for the ratioless gates which are particularly adapted to accommodate complex logic networks.
A no-delay, ratioless AND gate compatible with a four-phase, major-minor clocking scheme and a six-phase metal oxide semiconductor (MOS) system. The disclosed AND gate can be implemented by the interconnection of first and second field effect transistors having conduction paths thereof selectively connected between a respective input terminal and the output terminal of the AND gate to precharge and conditionally discharge the output terminal.
Circuitry having a unique strobing scheme to effectively drive both a light-emitting diode display and an associated keyboard directly from a single semiconductor chip. The circuitry accurately senses which of the keyboard keys is in a depressed condition in order that a suitable representation thereof may be displayed at an appropriate time.
A solid state logical "AND" circuit implementation in NMOS circuitry has clock pulse conditioning providing self booting voltage levels for ultra fast propagation times and minimal power dissipation, where memory row driver concepts are utilized and silicon area is minimized, and two, low impedance, non-overlapping clock pulses, normally present in the environment are utilized.
A solid state logical "OR" circuit for implementation with NMOS circuitry has self-booting clock pulse conditioning for ultra fast propagation times and minimal power dissipation, whereof memory row driver concepts are utilized and silicon area is minimized.
A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.
