A procedure for the parallel conversion of an analog signal to a cyclic binary code with one comparison to a threshold per channel, or bit, in which each channel is composed of an analog function generator, characterized by the fact that the transfer function of said generator is constructed in a piecewise-linear manner from a certain number of pairs of segments of straight lines, whose input/output slopes have equal absolute values and opposite signs, where in each pair the lower instantaneous value is selected by an operator MIN, of two arguments, and among all the lower instantaneous values thus selected, the greatest instantaneous value is selected by an operator MAX, of number of arguments equal to the number of pairs of segments that compose the said transfer function, in such manner that the value of the code is zero or one according to whether the instantaneous value at the output of the said function generator is below the value of the threshold of a comparator or above.

An analog-to-digital (A/D) converter which is capable of encoding each one of analog signal samples occurring at a high rate, such as 40 MHz (25 ns spacing), to eight digital output bits representing any one of 256 levels. Sixteen sixteen-level A/D converter sub-units each providing four binary output bits are connected in series across analog signal input terminals. A priority encoder and a multiplexer are responsive to the carry outputs of the A/D sub-units to produce four high-order digital output bits representing the rank of the sub-unit having a voltage range encompassing the voltage of an analog input signal. Gating means responsive to the four high-order output bits pass four low-order digital output bits from the one of the sixteen sub-units identified by the four high-order bits.

An indicator arrangement includes comparators for parallel comparison of an analog input voltage with digitalizing standard voltages to digitalize the input voltage and an indicator for indicating digitalized output. The arrangement is provided with a controller periodically switched between a first control state and a second control state. The controller in the first control state allows the comparators to perform comparison in a first voltage range of the analog input voltage while in the second control state it allows the comparators to perform comparison in a second voltage range of the analog input voltage. There is provided an encoder for coding the digitalized output of the comparators with a first coding mode in the first control state of the controller and coding the digitalized output of the comparators with a second coding mode in the second control state. The encoder is adapted to drive the indicator with a first or second mode according to the state of the controller.

An indicator arrangement includes comparators for parallel comparison of an analog input voltage with digitalizing standard voltages to digitalize the input voltage and an indicator for indicating digitalized output. The arrangement is provided with a controller periodically switched between a first control state and a second control state. The controller in the first control state allows the comparators to perform comparison in a first voltage range of the analog input voltage while in the second control state it allows the comparators to perform comparison in a second voltage range of the analog input voltage. There is provided an encoder for coding the digitalized output of the comparators with a first coding mode in the first control state of the controller and coding the digitalized output of the comparators with a second coding mode in the second control state. The encoder is adapted to drive the indicator with a first or second mode according to the state of the controller.

A parallel type A/D converter capable of operating at an extremely high speed with a high degree of accuracy and with low power consumption. A plurality of comparators each having a reference voltage corresponding to an assigned quantizing level are disposed in parallel with each other and divided into a plurality of comparator blocks or groups. A plurality of sub-comparators are provided so that prior to the comparison of the input signal by the comparators, the input signal is first compared with the reference voltages of the sub-comparators and in response to the output from the sub-comparator having the reference voltage comparable or corresponding to the incoming input signal, only the comparators in the comparator block or group associated with said sub-comparator are energized or enabled while the remaining comparators are kept de-energized or disabled, whereby a minimum power consumption may be attained.