A current mirror circuit of the present invention has the structure that the diode-connected second transistor is connected in series to the first transistor, the third and fourth transistors have bases which are respectively connected to the bases of the first and second transistors which are connected in series, and the collector of the fifth transitors, whose emitter and base are connected between the base and collector of the first transistor, is connected to the collector of the fourth transistor.

A current mirror circuit having high accuracy in its current mirror transfer ratio .lambda. even when constructed of P-N-P transistors. The circuit includes two stages each having three transistors of one conductivity type and a fourth transistor of a different conductivity type. Two of the like transistors of each stage have a common base electrode and the third like transistor is connected between the common electrode and a reference potential. The fourth transistor of each stage has its base connected to an individual one of the collectors of the base-connected transistors and its emitter connected both to a current source and the base of the third like transistor. The emitters of the base-connected transistors of the first stage and the collectors of the fourth transistors of each stage are connected to a power supply. The emitters of the base-connected transistors of the second stage are connected to the collectors of the base-connected transistors of the first stage. The collector of one of the base-connected transistors of the second stage is connected to a current source as an input and the collector of the other base-connected transistor of the second stage is connected to a load as the output.

Two gate-coupled pairs (12, 14; 16, 18) of MOS transistors are configured in a compound current mirror (10, 30) arrangement. Each pair includes an input (12; 16) and an output (14; 18) transistor. The output transistors are connected with their conduction paths in series between a source of output current a reference voltage node (22). Each of the input transistors is connected with its conduction path between the reference voltage node (22) and a separate current source (20, 24), with both sources supplying the same input current. One of the input transistors (12, 60) has a conduction path width-to-length ratio which is one-fourth that of the other one (16). This makes it possible to bias the output transistors with the minimum ON voltage for operation in the active region and thereby reduces power supply voltage overhead. A modified version (30) of the above arrangement includes, in addition, a transistor (32) for equalizing the drain-source voltage of the input and output transistors (16, 18) of an associated pair. An operational amplifier circuit (34) is described which is particularly adapted for the use of a compound mirror arrangement of two input transistors (54, 60), two output transistors (50, 52), and an equalizing transistor (56) in its differential input stage.

An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (OV) even if a reference voltage applied to generate a reference current does not reach OV. This circuit comprises cascode-connected first and second transistors cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.

The subject array structure provides a large current mirror array which generates a plurality of substantially equal output currents from high impedance sources in response to at least one input control current. This array structure reduces the control current deviation problem of prior art current mirror circuits.