A shift register stage comprises an MOS gating transistor having its drain and source electrodes connected respectively to an input node receiving pulses to be shifted through the stage and a gate electrode of an MOS amplifying transistor. A capacitor is connected between the gate and source electrodes of the amplifying transistor. The source electrode of the amplifying transistor constitutes the output of the stage and is connected to the drain electrode of a current source transistor having its source electrode connected to an earth line and its gate electrode connected to a reference potential. The gate electrode of the gating transistor is connected to receive a first series of clock pulses, and the drain electrode of the amplifying transistor is connected to receive another series of clock pulses in non-overlapping relation with the first series.
The shift register has a very low power consumption. Each cell of the shift register has two stages, each comprising an MOS structure (T.sub.1 -T'.sub.1) which has two principal electrodes (Z.sub.00, Z.sub.1) respectively forming the input (Z.sub.oo) and the output (Z.sub.1) of the stage, and two control electrodes (k.sub.1, k'.sub.1) one of which (k.sub.1) can be connected to a bias source (P) and the other of which (k'.sub.1) is connected to the output electrode (Z.sub.1), and a capacitor (C.sub.1), one plate (Z.sub.1) of which is connected to the said output electrode (Z.sub.1) and the other plate (C.sub.1) of which receives one of two periodic signals .phi..sub.1 (t) and .phi..sub.2 (t) in phase opposition. The register is especially useful in a frequency divider circuit.
There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.
A shift register includes at least one stage circuit that has at least three voltage control switches, a storage element, and a first clock signal, a second clock signal and a third clock signal to control various switches. Input signals are stored in the capacitor and sequentially transferred to the next stage. During transferring to the next stage, pixel switches of one row on the panel display are activated to receive information delivered from the data end for displaying on the pixels. The clock signals have the characteristics that the first clock signal, second clock signal and third clock signal are not at the same certain potential concurrently to prevent the switches of each stage (the second and third switches) from forming a DC path and burning out.
The main circuit of each stage of the high-reliability shift register circuit is composed of transistors, and the turn-on time for the four transistors are only 1.about.2 pulse time within one frame time. Transistors construct an inverter circuit which continuously offers a high-level supply voltage that controls activities of transistors so as to continuously offer a low-level supply voltage to the first node and the output terminal such that avoids the first node and the output terminal being in a floating state. Besides, one of the transistor acts as a charging circuit that extends the lifetime of another transistor. This circuit avoids the affection on the behavior of the shift register circuit that is caused by an a-Si (amorphous silicon) TFT under a sustained stress.
A non-inverting integrated circuit shift register stage is provided by a combination of four interconnected N-MOS transistors, connected to a two-phase clock pulse voltage source.
