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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to microprocessors and particularly to input/output
devices for providing data and/or address information to and receiving
output information from a digital data processing device.
2. Description of the Prior Art
Input/Output devices generally communicate with processing units over an
input/output bus over which is carried data and control signals for
utilization and operation of the respective devices Ordinarily, data and
control information is carried upon separate buses or connecting lines and
such control and data signals are usually terminated in a fixed control
element or data register within the central processor.
SUMMARY OF THE INVENTION
According to instant invention, an input/output device is connected to a
central processor by means of three buses. One is primarily used to
transmit input data to the processor, a second is primarily used to
transmit an address of an addressable element within the central
processor, and the third to receive output data from the central
processor. The instant invention provides a structure which is extremely
flexible in that the bus normally used for addressing an addressable
element within the processor may also be used to carry data, and neither
of the input buses is terminated at a specified location. For example,
data can be applied over both of the input buses, be operated upon in an
arithmetic and logic unit, and then outputted to the input/output device
on the third bus. Alternatively, the first bus may carry an address of a
memory or register element which is addressable, and the second bus may
carry data to be placed in the addressable element. Further, the address
bus may provide an address of an addressable element within the processor
from which information may be extracted and placed on the output bus.
An object of the invention is to provide a processor in which memory
operations are performed in a parallel mode.
A further object of the invention is to provide a processor in which Read
Only Memory operations are performed in a parallel mode.
A still further object of the invention is to provide a processor with a
single-phase fixed clock system.
A further object of the invention is to provide a processor with a double
interrupt system for both multiplexed and high speed data transfer for
real time operation.
A further object is to provide a microprocessor in which the control memory
can branch from one program segment to another without losing a machine
cycle time of the single phase clock.
Another object of the invention is to provide a processor capable of
extended or relative addressing of control or main memory in a single
machine cycle time.
A still further object of the invention is to provide a processor in which
the clock is single phase and controllable by the user to allow connection
of peripheral devices of varying speeds.
These and other objects, features, and advantages of the invention will
become more apparent when the following description is read in conjunction
with the drawings, in which:
FIG. 1 is an overall block diagram of the processor of the instant
invention.
FIG. 2 is a block diagram of the Micro Address Generator portion of the
processor.
FIG. 3 is a block diagram of the Microinstruction Processing portion of the
processor of the instant invention.
FIG. 4 is a block diagram of the Arithmetic and Logic Unit and General
Register Portion of the processor.
FIG. 5 is a diagram showing the information flow of the processor from a
general register through a function block and back to a general register.
FIG. 6 is a diagram of an alternate information flow path.
FIG. 7 is a diagram of a third information flow path wherein an IO register
is a source and either an IO or general register is the destination.
FIG. 8 is a block diagram of the Interrupt flow of the processor.
FIG. 9 is a diagram showing the locations of the micro fields in a
microinstruction used by the device of the instant invention.
FIG. 10 is a timing diagram showing the interrupt timing of the processor.
FIG. 11 is a table describing the functions of the ALU Select field of a
microinstruction.
FIG. 12 is a table showing bit position assignments of the B Bus.
FIG. 13 is a table describing the Microprogramming of Bus sources.
FIG. 14 is a table showing Word/Byte operation of the device.
FIG. 15 is a table showing the relative addressing feature of the device as
represented in a microinstruction.
FIG. 16 is a Timing diagram of the basic single phase clock and system
clock.
FIG. 17 is a logic block diagram of the address decoding logic for the
processor's IO and interrupt system.
FIG. 18 is a timing diagram of A Bus and B Bus timing.
FIG. 19 is a timing diagram of the C Bus timing.
FIG. 20 is a timing diagram of a typical multiplexed IO interrupt.
FIG. 21 is a block diagram of IO modules in a multiplexed IO interrupt
priority string.
FIG. 22 is a logic block diagram of the IO interrupt request logic of the
device of the invention.
FIG. 23 is a logic block diagram of the IO device address to A Bus logic.
FIG. 24 is a block diagram of an External Condition Logic Circuit.
FIG. 25 is a timing diagram of External Condition timing.
FIG. 26 is a block diagram of the Fast Interrupt Request and Response
to/from the processor.
FIG. 27 is the Fast Interrupt timing diagram for a Single Data Transfer.
FIG. 28 is a Fast Interrupt timing diagram for a Multiple Data transfer.
FIG. 29 is a block diagram showing essential elements of DMA.
FIG. 30 is a block diagram of a Multidevice Mode arrangement of processors
according to the invention.
FIG. 31 is a block diagram of Priority Control Logic of the device.
FIG. 32 is a block diagram of Request Control Logic.
FIG. 33 is a logic block diagram of the B Bus Control Logic.
FIG. 34 is a timing diagram of the Fast Interrupt Priority Control of the
device.
FIG. 35 is a block diagram of the IO Bus of the processor according to the
invention.
FIG. 36 is a block diagram showing the IO Enable Control logic.
FIG. 37 is a timing diagram of the IO Active signal.
FIG. 38 is a block diagram of the Multiplexer IO Interrupt.
FIG. 39 is a timing diagram of a Multiplexed IO Interrupt.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
In a preferred embodiment, a microprogrammed data processor may consist of
a device organized in a generalized three-bus structure where the
functional processing units are interconnected between operative buses by
means of tri-state logic.
Tri-state logic allows each unit to either drive, receive from, or present
a high impedance to the buses under control of a microcontrol register.
FIG. 1 shows such an arrangement wherein the A bus, B bus and C bus are
shown at 1, 2 and 3 respectively. Connecting the A bus 1 and the C bus 3
are a set of input/output registers 4 which are additionally connected to
an input/output bus 6 by means of a register bus selection multiplexer 8.
A set of general registers 10 is connected by means of their input to the
C bus and by means of their output to the A and B buses. As shown in FIG.
1, the general registers may be 16 bits wide, with the most significant 8
bit appearing on the left side of the diagram and the least significant 8
bit appearing on the right side thereof. It is possible to utilize a block
of 8 bit registers (using only the least significant 8 bits) by means of a
two to one multiplexer 12 which would divide the C bus' 16 bits into two 8
bit segments. Likewise, although the diagram indicates only the least
significant 8 bit segment connected to the A bus and B bus, with the
optional most significant 8 bit register block the resulting 16 bit words
may be directly placed on the A bus or B bus. Also shown associated with
the general register block is an adder 14 connected between the B bus and
the two to one multiplexer 12. The adder 14 allows an arithmetic operation
to be performed upon data as it is being passed through the general
register block from, for example, the B bus to the A bus. A translator 15
allows the storage of microinstruction sets corresponding to the
macroinstruction instruction set of a computer to be emulated.
A main memory and scratch pad memory 16 and 18, respectively, are shown
connected such as to receive data from the A bus and an address from the B
bus. The memory output is directed to the C bus 3. The scratch pad memory
18 may be used for intermediate storage beyond the limits of the 8 general
registers or for other purposes to be described later. The main memory can
be used to store data, results, microinstructions awaiting transfer to a
variable control memory, or microinstructions if the device is being used
in an emulation mode to emulate the macroinstruction set of another data
processing machine.
The microcontrol elements of the device include the micro-address register
20, the control memory 22 which may comprise a read-only memory and/or a
random access memory, and the microcontrol register 24 which holds the
current microinstruction while it is being executed. Also associated with
the microcontrol elements are a series of multiplexers 26, 28, 30, 32, 34
and 36. The multiplexers are used primarily for translating between
various address/data information bit widths. A push stack 38 and a stack
pointer counter 40 also associated with the microcontrol elements and
their functions will be described later. Similarly, decoder 42 will be
described in conjunction with the description of the microcontrol register
contents.
An arithmetic and logic unit 44 with its associated input and output
multiplexers 46 and 48, respectively, is capable of performing, in a
preferred embodiment, 32 arithmetic or 16 logical operations, taking its
two operands from the A bus and B bus and placing the results on the C
bus.
In very general terms, the operation of the machine is such that a 32-bit
microinstruction is divided into a number of fields which control all the
operations of the machine. For example, the microinstruction determines
the source of data for the A bus and B bus, whether it is to be an
input/output interface or a general register. It determines the function
to be performed in the arithmetic and logic unit on data from the A bus
and B bus, and it further determines that data from the A bus is to be
stored in scratch pad/main memory at an address contained on the B bus.
Complete definition of the microinstructions fields will be provided later
in this specification.
It is apparent, from a view of FIG. 1, that the microinstructions can
direct the flow of data through a variety of paths. Incoming data from the
input/output bus, for example, can be routed directly to scratch pads/main
memory or can be first operated on in the arithmetic and logic unit 44.
Results from the ALU 44 can be transmitted immediately by an input/output
register 4 to the input/output bus 6 or can instead be held in a general
register 10 pending further manipulation within the machine. Similarly,
information from scratch pad/main memory (18, 16) can be routed to the
input/output bus 6 or to a general register 10.
The general registers 10 may be used to buffer data between the C bus 3 and
the A bus 1 or B bus 2 for further processing or storage within the
machine. Similarly, the ALU 44 can be used as a path to move data
unchanged from the A bus 1 or B bus 2 to the C bus 3.
Thus, multiple fields enable the microinstruction to control a number of
operations and address civil locations simultaneously. A tightly packed
microinstruction provides parallel processing and results in efficient
machine utilization. It is apparent that, although not specifically shown
in FIG. 1 for purposes of clarity of description, a plurality of control
paths exist from the microcontrol register 24 to each of the devices which
has access to one or more of the buses.
It may also be noted that the generalized three-bus architeture of the
device makes it possible to add functions as the needs arise, such as, a
high-speed multiply/divide, square root, trigmetric functions, and code
conversions. The addition of a translator 15, together with an emulation
microprogram in the control memory permits the device to emulate a
computer instruction set.
System Organization
Three types of information are existant within the system. The basic
element of information is a 16-bit word in which the bit positions are
numbered from 0 through 15 as follows:
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Byte 0 Byte 1
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0 1 2 3 .vertline.4 5 6 7
0 1 2 3 .vertline.4 5 6 7
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The binary information in the system is generally expressed in hexidecimal
notation because four binary digits of information can be expressed by a
single hexidecimal digit. Thus, a byte can be expressed with a string of
two hexidecimal digits, a word with a string of four hexidecimal digits,
and a double word with a string of eight hexidecimal digits. For purposes
of this disclosure, a hexidecimal number is displayed as a string of
hexidecimal digits surrounded by single quotation marks and preceeded by
the letter X. For example, the binary number 01011010 is expressed in
hexidecimal notation as X 5A. Hexidecimal numbers are generally used to
denote addresses and data values. There are instances, however, in which
decimals numbers are more meaningful or are customary. Also, for purposes
of this disclosure, fixed-point data is expressed in two's complement
notation consisting of a 15-bit integer and a sign bit in the 0 position.
Logical operations assume that a logical data word format consisting of 16
bits without sign, is used.
A second class of information within the system is the micro-address. The
micro-address is 12 bits, capable of addressing up to 4,096 control memory
locations. The micro-address register (MAR) 20, push stack 38, and related
gating operations are on a 12-bit basis when a micro-address is routed
over one of the three buses 1, 2, 3, it occupies the least significant 12
positions of the 16 bit positions of each bus.
The third class of information in the system is the microinstruction, 32
bits in length. The control memory 22 and the microcontrol register (MCR)
24 both operate on a 32-bit basis. When a microinstruction is routed over
one of the buses, it is handled into 16-bit sections. The flow of
information within the device may be described in four categories called a
micro-address, microinstructions, data, and interrupt.
The basic microinstruction format is a 32-bit format subdivided into 11
micro-operational fields (micro OP fields) as shown below. This format
will be extensively discussed in a later following section of this
specification.
__________________________________________________________________________
0 31
__________________________________________________________________________
A
IO RA L RB A Bus B Bus C Bus/
Branch
Mult. Mult. Mult.
Mode Select
U Select
Cont. Cont. Regist.
Cont. uOP uOP uOP
Mode Cont. Fld. 1
Fld.
Fld.
__________________________________________________________________________
3
The micro-address information flow is shown generally in FIG. 2. Various
elemental blocks are numbered to coincide with the numbers originally
given in FIG. 1. Note the addition, however, of a clock control device 50
which is shown as driving the MAR 20. Although the clock control is shown
for only the one element 20, the equivalent clock function is assumed to
be applied in functional relation to all blocks in which the symbol .phi.
appears.
The micro-addresses are normally held in the MAR 20. From here they are
applied at .phi. at the 4:1 memory address multiplexer 28 to select the
control memory location in which a microinstruction is stored. The
micro-address in the MAR 20 can be changed in two ways:
1. Incremented to the next micro-address by the clock.
2. Jumped to another micro-address supplied from the C bus.
It should be noted that, for the purposes of the remainder of this
specification, where a slant line with a number immediately thereunder is
associated with a line on any of the figures, the number indicates the
number of wires connecting the associated elements. For example, between
the C bus and the micro-address register 20 a 12-wire cable is the
connective element.
The micro-address applied to control memory 22 can be multiplexed from 3
sources in addition to the micro-address register: A bus, B bus, and
interrupt logic. The interrupt logic 52 generates micro-address
corresponding to each interrupt.
When an immediate address is used and it is desired merely to increment the
micro-address register 20, bits 20 through 31 from the microcontrol
register 24 are used directly as the next micro-address. At the same time,
this immediate address is routed via bus A through the arithmetic and
logic unit (ALU) 44 with a one added thereto. The result is presented via
the C bus to the input of the MAR 20. The next system clock will cause
this value to be put into the MAR 20 allowing continuous simultaneous
fetch/execute cycles through the system. Relative micro-addressing will be
discussed in some detail later in this specification.
The current micro-address in the MAR 20 can be stored in the push-stack 38
and replaced with a micro-address from the C bus 3. Also, the
micro-address from the push stack 38 can be routed by the C bus 3 to the
micro-address register 20. At the same time the micro-address is stored in
the push stack, 6 status bits are entered into the push stack.
Instruction Flow
The microinstructions are stored in control memory. In the instant
embodiment, two types of control memory are shown, a read only memory 22
and a random access memory 23. It is also within the scope of the
invention to provide additional types of control memory such as an
electrically alterable memory. In addition, a separate memory may be
provided to perform such functions as diagnostics and field varification.
Micro-instruction processing is diagrammed in FIG. 3. When addressed by a
micro-address, a microinstruction is transferred from control memory 22 or
23 via a 2 to 1 multiplexer 32 to the microcontrol register MCR 24. A
microinstruction can also reach the MCR 24 from a maintenance control
panel via the C bus 3 and its associated 2 to 1 multiplexer 30 in 2 16-bit
increment.
In the case of the random access type control memory 23, a new
microinstruction can be written into the location addressed by the
micro-address. The new microinstruction is obtained in two 16-bit
increments from the A bus 1 over the 16-bit line shown in FIG. 3. A
microinstruction can be read out from any type of control memory via a two
to one multiplexer 30 in two 16-bit increments to the C bus 3.
From the MCR 24, the microinstruction is decoded to provide control signals
that direct the flow of data through the system as well be detailed later.
The last 12 bits of the microinstruction, when used as an immediate
micro-address are placed on the A bus 1 by means of the 12-bit line shown
in FIG. 3. Similarly, the last 8 bits of the microinstruction, when used
as an Emit field (to be discussed later) are placed on the B bus 2. The
three bits defining the bit switch/position are decoded in decoder 42 and
placed on the B bus.
With respect to timing, the first microinstruction is read from the control
memory 22, 23. When this microinstruction is clocked into the MCR 24, the
incrementor (ALU 44) is activated causing the MAR 24 to be incremented to
MAR+1.
Since there are no phases in the clock of the device, this new address is
immediately presented to the control memory 22 which reads the next
microinstruction to the input of the MCR 24. The next clock will save the
datum result input to the MCR 22 to the new microinstruction that was
waiting and increment the MAR to MAR+1. This process continues until a
micro-address other than a sequential sequence is needed.
Data Flow
Data flows through a number of paths and registers including the arithmetic
and logic unit ALU 44, general registers 10, input/output modules of
various kinds 4, scratch pad 18, main memory 16, and instruction
translator 15 if such a device is used to provide emulation of computer
macroinstructions.
Arithmetic and Logic Unit (ALU)
The ALU 44 accepts a byte or word from the A bus and B bus, performs
arithmetic or logic operations on the two operands and outputs the results
through a rotat/byte select logic 48 to the C bus 3 as shown in FIG. 4.
Operand word or byte selection, operations selection, and output shift or
byte select are all specified by control signals derived from the
microinstruction to be described later.
The input byte select gate 46a, 46b applies both bytes, the left byte, or
right byte, from the A bus to the A operand or from the B bus to the B
operand.
The arithmetic or logic operations is specified by the mode signal M (shown
above as the first of the 11 microoperational fields). One of 16
arithmetical and logic operations is selected by the four select lines
(shown as the second and fourth microoperational fields of the diagram).
Carry in, Cn, adds "one" the results.
The ALU result can be shifted left or right one bit or transferred direct
to the C bus. Also, the right byte of the results can be placed in the
left byte of the C bus.
General Registers
The general registers 10 provide a source for the A bus 1 and B bus 2 and
the destination for the C bus 3, as shown in FIG. 4. For example, the A
and B operands for the ALU 44 can be taken from general registers 10 and
the ALU results can be stored in a general register.
Additionally, one can be added to or subtracted from the value on the B bus
and the result stored in one of the general registers. This function is
performed by the add/subtract one function 14 connected from the B bus
through the 2 to 1 multiplexer 12 through a one to eight demultiplexer and
ultimately applied to the general register 10.
Status
Four of the six status bit to the ALU 44 are derived from arithmetic
operations, as defined below.
Carry: In word operation, the carry-out from the most significant bit of
the ALU (Bit 0) or, in byte operation, the carry-out from the most
significant bit of the byte (bit 8).
Overflow: An arithmetic operation on A and B operands results in a number
greater than the largest number that can be processed in the space
specified (word or byte). For example, in addition, overflow occurs if the
sum of two positive numbers is negative or the sum of two negative numbers
is positive, using two's complement format. Similarly, in subtraction,
overflow results if the subtraction of a negative number from a positive
number gives a negative number or if the subtraction of a positive from a
negative number gives a positive number. The overflow is indicated as a
status bit in register 62.
C bus equals 0: All bits of the C bus are 0. This status bit is carried in
register 60.
Sign: In word operation, the most significant bit of the word (bit 0) or,
in byte operation, the most significant bit of the byte (bit 8). This
status is carried in register 58.
Control Mode: A command decoded from the microinstructions sets and resets
this bit. It is used for additional control of an optional function such
as a macroinstruction translator. This register is not diagramed in FIG.
4.
Input/Output
Input/output modules 4 may be of various types to handle various modules
such as a teletype or paper tape. In general, the modules perform
functions of the following types:
1. Accept incoming data and place it on the A bus.
2. Transfer outgoing data from the C bus to the output.
3. Accept multiplexed general interrupts and place their identification on
the A bus.
The input/output will be extensively discussed in a latter portion of this
specification.
Scratch Pads/Main Memory
Referring to FIG. 1, data is written from the A bus into the scratch pad
18, main memory 16, at the location addressed by the B bus. Data is read
to the C bus 3 from the scratch pad 18, main memory 16 location addressed
by the B bus.
Translator
The translator 15 enables the device to emulate a computer instruction set.
This provides the means for translating a macroinstruction, taken from the
C bus into a micro-address .phi., placed on the A bus, that accessed the
first of a series of microinstructions in control memory 22 to implement
the macroinstruction. Moreover, in the case of a macroinstruction
containing an argument field, such as the address field used in
calculating direct or indirect memory locations, the translator transfers
the argument field to the B bus.
Maintenance Control Panel
The maintenance control panel (not shown) provides controls and indicators
that display the current status of the machine and make changes in that
status. The controls permit 16 data bits to be placed on the C bus, in the
microcontrol register, or (12 bits) in the micro-address register.
Interrupt and status bits are displayed continuously. Register or bus
contents can be displayed one at a time. The maintenance control panel
will be further defined in detail in a later section.
Information Flow: Summary
Information flow is the path which data takes from a general register
through some function lock back to a general register. A simplified view
of this flow is shown in FIG. 5.
The first level of gating (multiplexers 56) selects which register is to be
gated to the source buses A and B.
The second level of gating (byte select gates 46a, 46b,) selects which byte
on the A and B buses is to be presented to the ALU 44 to have some
function performed.
The third level of gating (shift/byte select 48) selects whether the output
of the ALU 44 is to be logically shifted left or right one bit position
and/or if the right byte should be moved to the left byte of the C bus
(destination bus).
Adding to this information flow is an alternate path that data may take
instead of through the ALU function logic. This alternate path is shown in
FIG. 6.
In FIG. 6, the first level of gating (multiplexers 56) select which
register is to be used as the data register (A and C buses) and which
register is to be used as the memory address register (B bus).
The second level of gating and the third level of gating are both disabled
(disconnected through the used of the tri-state logic previously
discussed) so that the output of the main memory can be connected directly
to the C bus (register destination bus).
The third information path allowed is shown in FIG. 7. The first level of
gating for the A bus (multiplexers 56) select, instead of a general
register 10 as its source, an IO register 4 to be gated onto the A bus.
The first level of gating for the B bus is free to select a general
register to be gated to the B bus.
The data flow can then be routed to the main memory 16 through the ALU 44
back to either the IO register 4 or general register 10 or from the main
memory 16 to the IO register 4. The third level of gating 48 is used only
when the ALU function is active.
Interrupt Flow
Seven interrupt lines originate in various parts of the system, as shown in
FIG. 8, all of which terminate at an interrupt register 70 when one or
more of the interrupt flip-flops is set, the micro-address of the
interrupt that has the highest priority is applied through the interrupt
micro-address and coder 52 to the memory address multiplexer 28 which then
addressed the control memory 22. The interrupts are diagramed in FIG. 8 in
order of priority from X 4 to X A. Each microaddress points to a
microinstruction specified by the system programmer initiating a procedure
that responds to that interrupt.
The contents of the interrupt register may be displayed on a maintenance
control panel 66.
The interrupts form the following functions:
Power Off: A logic signal from the power supply that indicates loss of
input power which in a short period of time after input power has dropped.
Power supply may be designed such that there is sufficient storage in the
power supply such that the voltage does not go out of regulation until
some period of time beyond that which the interrupt is activated.
Power On: A logic signal from the power supply that indicates the power is
on.
Fast Interrupt One: A logic signal from the input/output interface 4
directly to the interrupt register and used primarily for high-speed data
transfers to/from user logic via the IO interface 4 from/to scratch
pad/main memory 16, 18. The interrupt register returns a hardware response
to the IO interface.
Fast Interrupt Two: The same as fast interrupt one, except of lower
priority. One of the fast interrupts may be used to input data while the
other is used to output data. The fast interrupts will be described in
details in the later section:
Input/Output: A logic signal that indicates that a multiplexed input/output
interrupt is pending on one or more of the input/output interfaces. In
response to the signal, the system programmer requests the highest
priority I/O module 4 with an interrupt pending to put its address on the
A bus.
Error: A log | | |
