A buffer circuit interfaces between a bus request conductor coupled to a processor and a bus request terminal of a first circuit that is capable of asserting control over a data bus coupled to the processor. The buffer circuit includes a flip-flop that stores a state indicative of whether the first circuit is monitoring or driving its bus request terminal. The buffer circuit also includes circuitry that reproduces the logic level of the bus request conductor on the bus request terminal of the first circuit if the flip-flop contents indicate monitoring by the first circuit and reproduces the logic level of the bus request terminal on the bus request conductor if the flip-flop contents indicate driving by the first circuit.

An information transfer apparatus for connecting between plural channels and input/output control devices in a computer system, comprising a bundle of signal lines with which said channels are connected, said bundle of signal lines including plural signal lines provided respectively for said plural channels so as to effect the time-shared connection between said plural channels and input/output control devices therethrough.

A method and an apparatus to avoid a deadlock in a computer system with several busses connected by a bus adapter. If units of different busses of the computer system simultaneously start operations for which more than one bus is needed, it may come to a deadlock. By introducing a BUS SUSPEND signal to one of the busses and adapting the bus-protocol to honor this signal at distinct time slots, deadlock situations are avoided.

The digital bus is an asynchronous, linear, open-ended digital bus which is coupled to two or more computer/controllers. The bus includes address control circuit lines comprising a bus busy line used by a controller to assert a bus busy signal thereon to gain control of the bus, and to determine if another computer/controller is using the bus, a receiver computer/controller request line used by a controller for requesting permission to send data to another controller, and a receiver computer/controller ready line used by a controller for indicating that that controller is ready to receive data. Data control circuit lines are also provided comprising a data ready line used by a controller for placing a ready-to-send-data signal thereon and a data accept line used by a controller for placing a ready-to-accept-data signal thereon. Also, address bus circuit lines are provided comprising five binary address lines used by a controller for placing an address thereon, which address can have up to five bits. The bus further includes sixteen data bus circuit lines coupled to the two or more controllers. Data to be transferred by a controller is placed on the data circuit lines. A voltage source is coupled to the digital bus lines for pulling up the voltage on all the digital bus lines to the voltage level of the voltage source to make certain that clear signals are provided on the bus and noise problems are avoided. The controllers use the digital bus to asynchronously transfer data and to resolve contention problems between different controllers when they try to gain control of the bus at the same time.

A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.