An audio signal time-duration converter comprises a random access memory. The compression and expansion of input signals is effected by designating an address in the random access memory and assigning the designated address to a write mode or read mode. The address designation is effected either from an output from a write address counter which serves to count write clock pulses or an output from a read address counter which serves to count read clock pulses. However, in the event of overlap of the read and write clock pulses, the outputs are controlled exclusively by the write clock pulses. In addition, the time duration of the read and write clock pulses is made to be different so that both operations are ensured in a sequential manner in case of such overlap.
A time compression or expansion circuit for audio signals comprises an analog to digital converter (12), a random access memory (17), a latch circuit (18), a digital to analog converter (19), a clock pulse generator (13), a counter circuit (14), a data selector (16), and a timing controller (13). The timing controller (15) is supplied with a clock pulse from the clock pulse generator (13) and a timing signal from the counter circuit (18), and produces a series of writing-in pulses and a series of strobe pulses which exist alternately and have a common frequency regardless of the mode of compression or expansion or rate thereof. The analog to digital converter (12) converts an input audio signal (11) to a digital signal in response to a writing-in and reading-out switching pulse from the counter circuit (18). The random access memory (17) writes the signal from the analog to digital converter (12) in response to the writing-in pulse fed from the timing controller (15), into an address thereof designated by an address datum for writing-in, and reading a signal out of an address thereof designated by an address datum for reading-out in response to the strobe pulse of the common frequency in such a way that the written address of the memory is read multiple times or skipped being read according to the mode and rate. The latch circuit (18) holds the signal read out from the random access memory (17) in response to the strobe pulse from the timing controller (15).
A time domain panner samples a single analogue audio input signal and digitizes it into a 16-bit linear PCM representation which is fed into a memory array having a plurality of memory locations. A multiplexer feeds this memory array and continuously cycles in response to an address counter which repetitively counts to a maximum count. Address words produced by the address counter may address the array with or without add words, and a selected channel of the multiplexer points to a value stored in the memory array at a location established by the address counter plus an offset. Analogue output signals provided from left and right analogue output channels are time shifted selectively with respect to the analogue input signal and with respect to each other. Accordingly, analogue audio input signals are provided by a single signal source, fed into a memory array, and left and right analogue output channels are time-shifted with respect to the input excitement, and with respect to each other.
A method of and apparatus for time compression and changing the readout speed of a delta modulation encoded audio signal. The encoded audio signal has portions selectively deleted therefrom in accordance with detected zero crossovers of the same sign which occur in a predetermined timing sequence. The encoded audio signal which has had portions selectively deleted therefrom is decoded, with the undeleted decoded portions being joined. The undeleted portions have the same gain factor where joined, thereby eliminating step transients.
Audio data is converted into a digital format at a selectable conversion rate and applied through a microprocessor into memory storage. Stored data is selectively recalled and reconverted into an analog format for reconstruction into human speech at a processing rate independent of the input storage rate. The write pointer address and the read pointer address during the storage and retrieval of data are maintained within a selected address differential in accordance with the input data rate and the processing rate. To repeat the retrieval of particular stored data from selected address locations, the data input storage is interrupted thereby holding in memory a selected portion of previously stored data. The amount of data retrieved during the repeat process is varied by controlling the write pointer and the differential address between the write pointer and the read pointer.
A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.
