A three-terminal current amplifier having a current gain substantially independent of the forward current gains of its component FET's. First and second FET's have source electrodes connected to the common terminal of the amplifier. A third FET has its source electrode connected to the second FET drain electrode and has its gate and drain electrodes connected to the input terminal and the output terminal of the amplifier, respectively. The gate electrodes of the first and second FET's and the first FET drain electrode are coupled to the input terminal by a potential source providing an offset potential smaller than the source-to-gate potential of an FET, which permits the potentials required between the common terminal and each of the input and output terminals to be reduced as compared to prior art FET amplifiers of this sort.
This application is a continuation-in-part of United States Patent application Ser. No. 387,171, filed Aug. 9, 1973, now abandoned.
The present invention relates to a current amplifier using cascoded enhancement-type field-effect transistors in its output stage.
Current amplifiers using bipolar transistors and having current gains which are dependent upon the ratio of the transconductances of the transistors and substantially independent of the forward current gains of the transistors themselves are known in the prior art. Certain of these configurations developed for bipolar transistor circuits can be adapted for use with field-effect transistors (FET's) of the enchancement type--for example, metal-oxide silicon (MOS) field-effect transistors (MOSFET's). The configurations of principal interest are those in which the output stage uses cascoded transistors, since such an output stage provides the high output impedance generally desired of a current amplifier, despite the transistors not having optimally flat output circuit versus potential characteristics for fixed input circuit biasing conditions.
When realized with bipolar transistors, current amplifiers with cascode output stages need operating potentials no larger than one or two times the base-emitter offset potentials of a bipolar transistor (0.6 to 1.4 volts for silicon transistors). When these current amplifiers employ FET's, the required operating potentials are about one or two times as large as the gate to source potential of these devices.
Since the source-to-gate potential of a conventionally biased FET typically is several volts--for example, 4 to 4.5 volts for one milliampere current flow in enhancement type FET's designed to be compatible in processing with NPN bipolar transistors--the operating potentials required for these current amplifier designs are too large to be acceptable in many applications.
One important aspect of the present invention concerns biasing the output transistor of a cascode amplifier so the input transistor is operated with a smaller quiescent potential across its output circuit than across its input circuit. In a cascode connection of a common-source amplifier FET followed by a common-gate amplifier FET, the quiescent gate potential of the latter FET is chosen so the former FET is operated with lower quiescent source-to-drain potential than quiescent source-to-gate potential; this can be done without incurring voltage-limited saturation or seriously impairing transistor action. Alternatively, in a cascode connection of a common-emitter amplifier junction transistor followed by a common-base amplifier junction transistor, the quiescent base potential of the latter transistor is chosen to operate the former transistor with lower emitter-to-base potential than emitter-to-collector potential; this can be done without incurring saturation or seriously impairing transistor action. Either of these cascode arrangements can be operated without taking up so large a portion of available supply potential.
Another important aspect of the present invention is a three-terminal current amplifier having a current gain substantially independent of the forward current gains of its component FET's and having substantially reduced requirements insofar as input and output potentials are concerned. First and second FET's have source electrodes connected to the common terminal of the amplifier. A third FET has its source electrode connected to the second FET drain electrode and has its gate and drain electrodes connected to the input and output terminals, respectively, of the amplifier. The gate electrodes of the first and second FET's are coupled to the input terminal by means of a potential source providing an offset potential smaller than the source-to-gate potential of a FET, which permits the potentials required between the common terminal and each of the input and output terminals of the amplifier to be smaller than those required by prior art FET amplifiers of this sort.
Another aspect of the present invention is the use of this novel current amplifier as the active collector load of a bipolar transistor to achieve an amplifier stage having very high signal voltage gain.
A further aspect of the present invention is the use of an MOS inverter stage using complementary MOSFET transistors in direct-coupled cascade after the amplifier stage mentioned in the previous paragraph, to achieve an amplifier exhibiting not only high signal voltage gain but also (1) extended output signal swing capabilities for restricted power supply potentials and (2) decreased source impedance in its output circuit.
A novel, precise current mirroring technique for depletion-mode field effect transistor technology uses a diode level-shifting circuit between the drain and the gate of a first depletion-mode Field Effect Transistor (FET) to keep its gate voltage below its drain voltage. The gate of the first depletion-mode FET is connected to the gate of a second depletion-mode FET. A current source is used to compensate for the current drawn by the level-shifting circuit. The current source preferably includes a FET and at least one Schottky diode.
The input offset potential of a transistor amplifier exhibited by a grounded-emitter bipolar transistor or a grounded source enhancement-mode field effect transistor can be too large for certain applications. A preceding differential-input amplifier overcomes this problem.
An improved current amplifier, of the type having input, output and common terminals and which is subject to having widely dissimilar voltages at its input and output terminals has field-effect master and slave transistors formed in a region of semiconductor substrate having an impurity concentration gradient such that the material resistivity increases in a direction into the substrate and provided with relatively deep drain extensions.
A folded-cascode amplifier arrangement includes first and second transistors of complementary conductivity type and a constant current generator for supplying quiescent current thereto. Signal current flowing in the first transistor is coupled to the second transistor through current steering at the interconnection between their main conduction paths. The load means for the second transistor includes a cascode-connected third transistor for supplying load current thereto, which third transistor substantially increases the resistance of the load for correspondingly increasing the voltage gain of the amplifier arrangement. The amplifier voltage gain transfer function exhibits a frequency response dominated by a single pole.
A hydrophone and preamplifier are coupled to receive signals representative f impinging acoustic energy. At the other end of a long length of two conductor coaxial cable, a receiver section provides representative voltage signals for following processing circuitry. DC power is fed to the preamp section along the single cable which also transmits the information current signals back to the receiver. The receiver section is designed to present a very low input impedance to enable the swamping out of the capacitive reactance introduced by the long cable. This allows the use of a long coaxial towing cable without introducing any appreciable frequency response degradation. Suitable electronic interconnection ensures that the preamplifier output signal is not affected by the supply voltage back at the receiver section and moderate potential variations between the cable ends do not introduce spurious noise components.
