Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive pulse coded modulation (PCM) output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing one adder running three times faster than the sigma-delta clock for loading one of three accumulators. As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order in which the accumulators are loaded by the adder each PCM sampling time enables having zero as the last coefficient value to add to the accumulator, the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.

To minimize distortion, a sequence of phase modulated signal elements (data symbols) are combined in accordance with a predetermined shaping (weighting) function by a transversal filter augmented with a baud rate control circuit. The transversal filter includes a plurality of multipliers, located at taps along a delay line, forming products between data symbols and coefficients representing segments of the predetermined weighting function. The baud rate control circuit shifts the phase of the delayed data symbols and delivers these "extended" data symbols to certain multipliers. By digitally processing segments of the weighting function and portions of an overall data symbol this invention yields to compact construction.

A digital filter for generating digital output signals from information signals in accordance with a predetermined transfer characteristics includes a coefficient number generator for supplying digital numbers which indicate the values of coefficients which represent the transfer characteristic. The coefficient number generator includes a device for storing increments of successive coefficient values in numerical form and a decoder connected thereto for recovering the coefficient numbers from the numbers stored in the storage device.

A method and system of accurately processing a discrete time input signal having a first clock rate into a discrete time output signal having a second clock rate is presented. The method includes delta filtering the input signal to produce an intermediate signal having the first clock rate and delta interpolating the intermediate signal to produce the output signal. Delta filtering includes calculating an input delta signal by subtracting an initial value from the input signal, generating a filtered delta signal, and adding the initial value to the filtered delta signal. Delta interpolating includes upsampling the intermediate signal to the second clock rate, calculating an upsampled intermediate delta signal by subtracting an initial value from the upsampled intermediate signal, filtering the intermediate delta signal, and adding the initial value to the filtered intermediate delta signal. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

A digital filter includes a pair of serially connected second order sections (200 and 260), each of which includes delay elements arranged to store the number of bits contained in two complete input words. Each filter section also includes simple logic (220, 230, 270 and 280) comprising adder circuits and inverters but no multipliers. The logic combines outputs from the delay element with the filter input to form an intermediate signal which is applied to the input of the delay element. The intermediate signal is also combined with yet other outputs from the delay element to form the filter output. To eliminate clocking complexity within the filter, the logic is not preset or cleared between each input word. Instead, the word length is intentionally increased, and the sign bit of each intermediate word is intentionally repeated as the word is processed in the filter, the extra bits acting as an inter-word buffer and serving to protect against spurious overflow and limit cycle oscillations.