In a circuit arrangement for establishing and terminating a connection in a subscriber communication system, the arrangement including a data transmission device arranged to be connected to an associated subscriber line of the system and including a data terminal, a line connection device fed by the terminal, an automatic dialing device, a current supply fed through the subscriber line and a control device for performing and monitoring the sequence of individual operating states of the data transmitting device, a memory unit is connected for storing a representation of at least one operating state of the data transmission device.

An electronic register for an electric meter includes a non-volatile storage into which data is written upon the detection of an impending power outage. A sufficient quantity of electric energy is normally stored in a capacitor to continue operation of the electronic register for a long enough period of time to complete the writing of data to the non-volatile storage. In order to prevent writing of the data to non-volatile storage in the presence of noise or momentary power outages, when the voltage in the capacitor decays to a point which indicates an impending power outage, a timer is started. If the voltage is not restored before the end of the timing cycle of the timer, then the data is written to the non-volatile storage. If the voltage is restored before the end of the timing cycle, then writing of the data to the non-volatile storage is prevented.

An arrangement for storing user programmed system timing information in a microprogrammable system in the event of a power outage. The system includes a static random access memory (RAM) for periodically storing microprocessor-generated timing information and an electrically erasable programmable ROM (EEPROM) which is coupled to the static RAM for the temporary storage of this information in the event of a power outage. Also provided in the system is a power down sensor responsive to an AC-coupled power supply for detecting power loss to the system. When the input voltage drops below a predetermined value, the contents of the static RAM are automatically transferred to the nonvolatile EEPROM. When system input power is restored, the stored contents of the nonvolatile EEPROM are automatically retransferred back to the static RAM for use by the microprocessor permitting the resumption of system operation as previously programmed on a time-shifted basis where the time shift equals the duration of the power outage. The system is particularly adapted for use with a user-programmed device, such as a television receiver or a video cassette recorder, in an environment where power outages of very short duration randomly occur. The present invention permits such a system to resume programmed system operation following resumption of power to the system without employing the combination of a battery, an oscillator, a CMOS RAM and appropriate recharging circuitry, as generally utilized in such systems.

A power failure detection and restart system for use with a microprocessor (microcomputer) control system includes first and second cascaded voltage comparators, the first of which responds to a drop in the supply voltage supplied to the microprocessor to produce an output pulse causing a software freeze of the microprocessor. The microprocessor operates in response to the software freeze pulse to transfer the contents of certain registers thereof to a battery protected memory for temporary storage therein. A positive feed-back circuit is used on the first voltage comparator to insure its rapid and complete change of state; and this change of state signal is applied through a time delay circuit to the second voltage comparator, which produces an output signal a predetermined time after the software freeze pulse is obtained from the first voltage comparator to reset the microprocessor to an initial circuit condition. Built in hysteresis in the system is employed; so that when the power once again rises above the level sufficient to properly operate the system, the first and second voltage comparators are turned on in the same sequence they were turned off to re-establish operation of the microprocessor which picks up its routine at the point the interruption took place.

A method and apparatus for powering down a computer system while saving the state of the system at power down is disclosed. The system maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at that same point at a later time. The time at which the system may be powered down and then powered back up again is totally arbitrary and depends only upon the user of the system. At the time the system is powered off, the contents of all active registers as well as the states of all I/O devices in the system are stored in a special save area of system memory. This special save area is provided with power during the suspended time in order to retain the state of the system at the time it was powered down. By using this special save suspend area, the main memory area of the system is available to any application programs independently of the system save memory requirements. Additionally, the system may be powered on and off under software control thereby providing the capability for unattended system operation using an alarm function.