Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary inputs (PI) to the logic network to be tested while the output of several of the logic blocks are also outputs (PO) of the logic network to be tested. However, the inputs and outputs of many logic blocks of the network to be tested are inaccessible since as is well known in large scale integration (LSI), a large number of internal circuit nodes cannot be probed directly. In accordance with the present disclosure, such a logic network to be tested is simulated and each of the logic blocks as well as the inputs and outputs of each of these logic blocks is uniquely defined. A first test pattern is then applied to the primary inputs (PI) of the network to set the logic levels on these primary inputs to known values. A particular one of the logic blocks within the network is then selected and a specific fault associated with the particular logic block is assumed. A test value for this assumed specific fault in the simulated network is then propagated towards a primary output, one logic stage at a time, by backtracing through the network to a primary input to determine which primary input value must be altered in order to propagate the assumed fault towards a primary output. Without developing an entire test sequence, analysis at each step determines whether the test is in fact progressing by propagating the test value through the network toward the primary input. The term "test value" is defined as the binary vaue of a point within the logic network that is opposite from that expected in the absence of the assumed fault. When a "test value" has been successfully propagated to a primary output (PO), then it is known that the particular sequence of input test patterns is suitable for detecting the specific fault assumed in the simulator. By applying the same sequence of test patterns to the actual network under test and comparing the primary outputs of the network under test and primary outputs of the simulated network, it is determined whether the particular assumed simulated fault is actually present in the network under test. On a real time basis, each time a successive pattern is applied to the simulated network, it is analyzed, and if found unsuitable, it is discarded and a different changed input pattern is sought by backtracing to a primary input through a different path. Each successive pattern is applied to the network under test only if found to be valid.
A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described. With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences so that when they are applied, all outputs of embedded RAMs attain known values.
A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.
A test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCO.sub.f and a continuous cyclic logic value CV.sub.f at a preselected line G.sub.f in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CT.sub.f by the use of the controllability cost CCO.sub.f and the continuous cyclic logic value CV.sub.f for each subservient pattern signal. A selector selects from the set of subservient pattern signals a subservient pattern signal that produced a minimum evaluation cost CT.sub.f, test pattern memory stores the selected subservient pattern signal as one test pattern and assigns the selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.
A scheme for generating test patterns for logic circuits which can generate the test patterns effectively and efficiently by making the assignments of the fewer logic values at earlier stages, so as to reduce the number of backtracking operations required. A test pattern for a logic circuit given by primary input logic values for setting a logic value of a specified signal line within the logic circuit at a specified level is generated by: checking whether a fault can be propagated to the specified signal line or not; deriving other signal lines whose logic values are uniquely determinable from the specified level of the specified signal line, only when it is judged that the fault cannot be propagated to the specified signal line; judging whether the primary inputs are contained among the derived other signal lines; and making an assignment of the specified level to the specified signal line, and setting the uniquely determinable logic values for those of the other signal lines which are judged as the primary inputs as the primary input logic values giving the test pattern.
The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.
