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Claims  |
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The embodiments of the invention in which an exclusive property or
privilege is claimed are defined as follows:
1. A harmonic-reduced variable frequency and variable voltage power supply
for a three phase a.c. motor (M) comprising, in combination,
a d.c. source (BR),
a three phase inverter bridge (INV) including a plurality of power
transistors (1A, 1B, 1C, 2A, 2B, 2C) between said d.c. source and said
motor,
means (SPEED POT) for deriving an analog speed signal indicative of desired
speed of said motor,
oscillator means (VCO) for providing a train of clock pulses (f1) whose
frequency is a function of the magnitude of said analog speed signal,
resettable volt/hertz integrator means (RI) receiving as an input the
output voltage from said inverter bridge for integrating said output
voltage with respect to time and for deriving a train of ramp pulses
(v.sub.c14) which are synchronized to said clock pulses and whose
instantaneous magnitude varies with time as a function of the volt/hertz
integral,
a first comparator (LC1) for comparing said volt/hertz integral to a first
reference voltage and for deriving a first control pulse (HVT) when the
voltage of each said ramp pulse becomes equal to said first reference
voltage,
a second comparator (LC2) for comparing said volt/hertz integral to a
second reference voltage which is of lower magnitude than said first
reference voltage and for deriving a second control pulse (LVT) when the
voltage of each said ramp pulse becomes equal to said second reference
voltage,
Or-circuit means (D27, D28, Q13) for disabling said integrator means when
said first control pulse (HVT) is generated and for holding said
integrator means disabled until the succeeding clock pulse (f1) is
generated or for disabling said integrator means when the succeeding clock
pulse is generated,
a three phase generator (GEN) for deriving three phase reference waves (A,
B, C) displaced 120 electrical degrees apart having a 360 electrical
degree period equal to the time interval required to generate a
predetermined number of said clock pulses with positive and negative half
cycles, each of said reference waves being associated with one phase of
said bridge,
modulation means for controlling the fundamental output voltages of
individual phases of said three phase inverter bridge in accordance with
said three phase reference waves (A, B, C) and including means for pulse
width modulating the output power of said individual phases of said bridge
by variable width PWM pulses whose leading edges are established by said
clock pulses, said pulse width modulation means regulating the termination
of PWM pulses which occur during the first 30 degrees and during the last
30 degrees of the positive half cycles of the associated reference waves
as a function of said second control pulses (LVT) and regulating the
termination of other PWM pulses in said positive half cycle as a function
of said first control pulses (HVT), whereby the magnetic flux in said
motor is constant regardless of speed and harmonics are reduced in the
inverter bridge output voltages.
2. A power supply in accordance with claim 1 wherein said pulse width
regulating means modulates the output power of said bridge phases during
the negative half cycles of the associated reference waves by PWM pulses
which are the complements of those provided during the positive half
cycles.
3. A power supply in accordance with claim 2 wherein said pulse width
modulation means provides maximum duty PWM pulses for approximately 60
degrees adjacent the midportion of the positive half cycles of the
associated reference waves and provides minimum duty PWM pulses for
approximately 60 degrees adjacent the midportion of the negative half
cycles thereof.
4. A power supply in accordance with claim 1 wherein said inverter bridge
(INV) has three phase legs (e.g., .phi..sub.1 ) each of which comprises
first (e.g., 1A) and second (e.g., 1B) transistors connected in series
across said d.c. source (BR) and first (e.g., 1AD) and second (e.g., 1BD)
feedback rectifiers connected in inverse parallel relation respectively
with said first and second transistors, and said pulse width modulation
means switches said first (e.g., 1A) and second (e.g., 1B) transistors in
each said phase leg in opposition so that one is off while the other is
conducting.
5. A power supply in accordance with claim 4 wherein said first transistor
(e.g., 1A) in each said phase leg is coupled to the positive side of said
d.c. source, and said pulse width modulation means controls chopping of
current by said first transistor during the positive (A) and negative (A)
half cycles respectively of the corresponding phase reference wave by
trains of transistor switching pulses (1a, 1b) which are complements of
each other.
6. A power supply in accordance with claim 5 wherein said pulse width
modulation means terminates the PWM voltage pulses conducted by said first
transistor (e.g., 1A) during the first 30 degrees and during the last 30
degrees of the positive half cycle (e.g., A) of the corresponding phase
reference wave approximately at said second control pulses (LVT) to
thereby derive narrower (b width) PWM pulses and also controls said first
transistor during the first 30 degrees and during the last 30 degrees of
the negative half cycle (A) of said corresponding phase reference wave by
pulses (w-b) which are the inverse of those applied to said first
transistor during said positive half cycle of said corresponding reference
wave.
7. A power supply in accordance with claim 6 wherein said pulse width
modulation means terminates other PWM voltage pulses conducted by said
first transistor during the portion of said corresponding phase reference
wave positive half cycle occurring between said first 30 degrees and last
30 degrees approximately at said first control pulses (HVT) to thereby
derive wider (a width) PWM pulses and controls said first transistor
during the portion of said reference wave negative half cycle (A) between
said first 30 degrees and last 30 degrees by pulses which are the
complements of those applied to said first transistor during such portion
of said reference wave positive half cycle.
8. A power supply in accordance with claim 7 wherein said pulse width
modulation means provides maximum duty cycle PWM pulses from said first
transistor during approximately 60 degrees of said positive half cycle
(e.g., A) of the corresponding phase reference wave and provides minimum
duty cycle PWM pulses during approximately 60 degrees of the negative half
cycle (e.g., A) thereof.
9. A power supply in accordance with claim 8 wherein said pulse width
modulation means provides maximum duty cycle PWM pulses from said first
transistor (e.g., 1A) during approximately 60 degrees midway of said
positive half cycle (e.g., A) of said corresponding phase reference wave.
10. A supply power in accordance with claim 4 and including interval
generator means (IG) for deriving three trains of step controlling signals
(H1, H2, H3) each of which corresponds to one of said phase reference
waves and spans respective zero crossings of said corresponding phase
reference wave.
11. A power supply in accordance with claim 10 and including volt-second
switch means (VSS) for deriving three trains of duty cycle regulating
pulses (VT1, VT2, VT3) each of which is associated with one phase (e.g.,
.phi..sub.1) of said inverter bridge and the corresponding reference wave
(e.g., A) and whose leading edges are at said first control pulse (HVT)
when the corresponding step controlling signal (e.g., H1) is absent and at
said second control pulse (LVT) when it is present, the trailing edges of
said duty cycle regulating pulses (e.g., VT1) being at the succeeding
clock pulses (f1).
12. A power supply in accordance with claim 11 wherein said volt-second
switch means (VSS) provides a signal (VT) to said OR-circuit means
(D27-D28) to reset said volt/hertz integrator means (RI) in response to
each said first control pulse (HVT).
13. A power supply in accordance with claim 12 wherein said step
controlling signals are of approximately 60.degree. width.
14. A power supply in accordance with claim 11 and including modulation
logic means (ML) for generating three trains of transistor switching
pulses (1a, 2a, 3a) each of which is associated with one phase of said
inverter bridge and regulates the switching of said first transistor
(e.g., 1A) in said one phase (e.g., .phi..sub.1) and which follows the
complement (e.g., VT1) of said corresponding train of duty cycle
regulating pulse (VT1) during the positive half cycle (A) of the
corresponding phase reference wave and follows said train of duty cycle
regulating pulses (VT1) during the negative half cycle (A) of said
corresponding phase reference wave.
15. A power supply in accordance with claim 14 wherein said modulation
logic means also generates three trains of pulses (1b, 2b, 3b) which are
the complements of said trains of transistor switching pulses (1a, 1b, 1c)
and each of which (e.g., 1b) regulates the switching of said second
transistor (e.g., 1B) in the associated phase leg (e.g., .phi..sub.1) of
said bridge inverter.
16. A power supply in accordance with claim 14 wherein said modulation
logic means also superimposes a pulse of approximately 60.degree. duration
on said train of transistor switching pulses (e.g., 1a) during the
positive half cycle (A) of the corresponding phase reference wave and
omits pulses for approximately 60.degree. from said train of transistor
switching pulses (1a) during the negative half cycle (A) of said
corresponding phase reference wave.
17. A variable frequency and variable voltage power supply in accordance
with claim 1 and including motor stator voltage versus frequency setting
means (R59) for selectively adjusting the slope of said ramp pulses
(v.sub.c14) to thereby vary the frequency range over which the maximum
output torque of said motor is approximately constant.
18. A variable frequency and variable voltage power supply in accordance
with claim 1 and including harmonic setting means (R77) for selectively
varying the magnitude of said second reference voltage to thereby regulate
the percent of fifth and seventh harmonics in the currents to said motor.
19. A variable frequency and variable voltage power supply in accordance
with claim 4 and including
a frequency divider (DIV) for providing a first train of timing pulses
(f1'/6) whose frequency is equal to the quotient of the frequency of said
clock pulses divided by an integer, and wherein said three phase generator
(GEN) includes a plurality of master-slave flip-flops (FF1, FF2, FF3 -
FIG. 9) arranged in a ring and each of which receives said first timing
pulses (f1'/6) on its clock input.
20. A variable frequency and variable voltage power supply in accordance
with claim 19 wherein said frequency divider provides first and second
trains of timing pulses (f1'/6, f1"/6) each of whose frequency is equal to
the quotient of the frequency of said clock pulses divided by an integer
and the timing pulses of said first and second trains are displaced
180.degree. in phase, and including interval generator means (IG)
receiving said second train of timing pulses (f1"/6) and said three phase
reference waves (A, B, C) as inputs for deriving three sets of step
controlling signals (H1, H2, H3) each of which corresponds to one of said
phase reference waves (A, B, or C) and spans respective positive-going and
negative-going zero crossings of said corresponding phase reference wave.
21. A variable frequency and variable voltage power supply in accordance
with claim 20 and including volt-second switch means (VSS) for deriving
three trains of duty cycle regulating pulses (VT1, VT2, VT3) each of which
trains is associated with one phase of said bridge inverter (e.g.,
.phi..sub.1) and the corresponding phase reference wave (e.g., A), the
leading edges of said duty cycle regulating pulses being at said first
control pulse (HVT) when the corresponding step controlling signal (e.g.,
H1) is absent and at said second control pulse (LVT) when it is present,
the trailing edges of said duty cycle regulating pulses (VT1, VT2, VT3)
being at the succeeding clock pulses (f1).
22. A variable frequency and variable voltage power supply in accordance
with claim 21 and including modulation logic means (ML) receiving said
three phase reference waves (A, B, C) and said trains of duty cycle
regulating pulses (VT1, VT2, VT3) as inputs for generating three trains of
transistor switching pulses (1a, 2a, 3a) each of which corresponds to one
of said reference waves (e.g., A) and to an individual phase (e.g.,
.phi..sub.1) of said bridge inverter for regulating the switching of said
first transistor (e.g., 1A) of said corresponding phase, each of said
train of transistor switching pulses (e.g., 1a) following the
corresponding train of duty cycle regulating pulses (VT1) during the
negative half cycle (A) of the corresponding phase reference wave and
following the complement of said train of duty cycle regulating pulses
(VT1) during the positive half cycle (A) of the corresponding phase
reference wave.
23. A variable frequency and variable voltage power supply in accordance
with claim 22 wherein said modulation logic means (ML) for generating said
trains of transistor switching pulses (VT1, VT2, VT3) also superimposes a
pulse of approximately 60.degree. duration on said complement of said
train of duty cycle regulating pulses (e.g., VT1) during the positive half
cycle (e.g., A) of the corresponding phase reference wave and omits pulses
for approximately 60.degree. from said train of duty cycle regulating
pulses (e.g., VT1) during the negative half cycle (e.g., A) of said
corresponding phase reference wave.
24. A power supply in accordance with claim 23 wherein said modulation
logic means (ML) also generates the complements (1b, 2b, 3b) of said
trains of transistor switching pulses (1a, 2a, 3a) and each of which
complement (e.g., 1b) regulates conduction by said second transistor
(e.g., 1B) in the corresponding phase leg of said bridge inverter.
25. A power supply in accordance with claim 1 wherein the magnitude of said
second reference voltage is equal to approximately 0.732 times the
magnitude of said first reference voltage.
26. A harmonic-reduced, variable frequency and variable voltage power
supply for a three phase a.c. motor comprising, in combination, a three
phase bridge inverter having three phase legs each of which comprises
first and second transistors connected in series across a d.c. power
source and first and second feedback rectifiers connected in inverse
parallel relation with said first and second transistors respectively,
oscillator means for generating a succession of clock pulses whose
frequency is a function of an analog speed signal, resettable volt/hertz
integrator means for deriving a train of ramp pulses which are
synchronized to said clock pulses and whose instantaneous magnitude varies
as a function of the integral of the output voltage of said bridge
inverter with respect to time, first and second comparators for deriving
first (HVT) and second (LVT) control pulses when the voltage of each said
ramp pulse becomes equal respectively to first and second reference
voltages of different magnitude, means for disabling said integrator means
at said first control pulse and for holding it disabled until the
succeeding clock pulse, three phase generator means for deriving three
phase reference waves (A, B, C) displaced 120.degree. whose edges are
synchronized to said clock pulses and each of which has a period equal to
the time required to generate a predetermined number of said clock pulses
and has positive and negative half cycles, interval generator (IG) means
for deriving three trains of step controlling signals (H1, H2, H3) each of
which corresponds to one of said phase reference waves and which step
controlling signals span respective zero crossings of said corresponding
phase reference wave, volt-second switch means for deriving three trains
of duty cycle regulating pulses (VT1, VT2, VT3) each of which is
associated with one phase of said inverter bridge and which duty cycle
regulating pulses have leading edges at said first control pulse HVT when
the corresponding step controlling signal is absent and at said second
control pulse (LVT) when the corresponding step controlling signal is
present and whose trailing edges are at the succeeding clock pulse, and
modulation means for generating three trains of transistor switching
pulses (1a, 1b, 1c) each of which regulates the switching of said first
transistor in one phase of said inverter bridge and which follows the
complement (e.g., VT1) of said train of duty cycle regulating pulses
during the positive half cycle (e.g., A) of the corresponding phase
reference wave and follows said train (e.g., VT1) of duty cycle regulating
pulses during the negative half cycle (e.g., A) of the corresponding phase
reference wave.
27. A power supply in accordance with claim 26 wherein said modulation
logic means also derives the complements of said trains of transistor
switching pulses and each said complement regulates conduction of said
second transistor in the associated phase of said inverter bridge.
28. A harmonic-reduced variable frequency and variable voltage power supply
for a three phase a.c. motor (M) comprising a three phase bridge inverter
bridge (INV) having three phase legs each of which comprises first (e.g.,
1A) and second (e.g., 1B) transistors connected in series across a d.c.
power source (BR) and first (1AD) and second (1BD) feedback rectifiers
connected in inverse parallel relation with said first and second
transistors respectively, oscillator means (VCO) for generating a
succession of clock pulses (f1) whose frequency is a function of an analog
speed signal, resettable volt/hertz integrator means (RI) for deriving a
train of ramp pulses (v.sub.c14) which are synchronized to said clock
pulses and whose instantaneous magnitude varies as a function of the
integral of the output voltage of said bridge inverter with respect to
time, first (LC1) and second (LC2) comparators for deriving first (HVT)
and second (LVT) control pulses when the voltage of each said ramp pulse
becomes equal respectively to first and second reference voltages, means
(Q13) for disabling said integrator means at said first control pulse and
for holding it disabled until the succeeding clock pulse, a frequency
divider (DIV) for generating trains of first (f1'/6) and second (f1"/6)
timing pulses each of whose frequency is equal to the quotient of the
frequency of said clock pulses divided by an integer and which are
displaced 180.degree. in phase, three phase generator means (GEN)
receiving said train of first timing pulses (f1'/6) as an input for
deriving three phase reference waves (A, B, C) displaced 120.degree. whose
edges are synchronized to said clock pulses and each of which has a
360.degree. period equal to the time required to generate a predetermined
number of said clock pulses and having positive and negative half cycles,
interval generator means (IG) receiving said train of second timing pulses
(f1"/6) and said three phase reference waves (A, B, C) as inputs for
deriving three trains of step controlling signals (H1, H2, H3) each of
which corresponds to one of said phase reference waves (A, B, C) and spans
respective zero crossings of said corresponding phase reference wave,
volt-second switch means (VSS) for deriving three trains of duty cycle
regulating pulses (VT1, VT2, VT3) each of which is associated with one
phase of said inverter bridge and which duty cycle regulating pulses have
leading edges respectively at said first control pulse (HVT) when the
corresponding step controlling signal (e.g., H1) is absent and at said
second control pulse (LVT) when the corresponding step controlling signal
is present and whose trailing edges are at the succeeding clock pulse, and
modulation means (ML) for generating three trains of transistor switching
pulses (1a, 1b, 1c) each of which regulates the switching of said first
transistor (e.g., 1A) in one phase (e.g., .phi..sub.1) of said inverter
bridge and which follows the complement (e.g., VT1) of said train of duty
cycle regulating pulses during the positive half cycle (e.g., A) of the
corresponding phase reference wave and follows said train of duty cycle
regulating pulses (VT1) during the negative half cycle (A) of the
corresponding phase reference wave.
29. Chopping pulse generating means for an n-phase bridge inverter having
first and second series-connected transistors in each phase leg adapted to
be connected across a d.c. source, comprising, in combination,
oscillator means for generating a succession of clock pulses (f1) whose
frequency is a function of an analog speed signal,
resettable volt/hertz integrator means (RI) for deriving ramp pulses
(v.sub.c14) which are synchronized to said clock pulses and whose
instantaneous magnitude varies as a function of the integral of the output
voltage from said inverter with respect to time,
first (LC1) and second (LC2) comparators for deriving first (HVT) and
second (LVT) control pulses when said ramp pulses become equal
respectively to first and second reference voltages of different
magnitude,
n-phase generator means (GEN) for deriving n-phase reference waves (A, . .
. N) displaced 360/n degrees apart having edges synchronized to said clock
pulses (f1) and each of which is associated with one phase leg of said
inverter bridge and has a 360.degree. period which includes a
predetermined number of said clock pulses and has positive and negative
half cycles,
interval generator means (IG) for deriving n trains of step controlling
signals (H1, . . . Hn) each of which corresponds to one of said reference
waves (A, . . . N) and spans respective zero crossings thereof,
volt-second switch means (VSS) for deriving n trains of duty cycle
regulating pulses (VT1, . . . VTn) each of which corresponds to one of
said reference waves (A, . . . N) and which pulses have leading edges at
said first control pulse (HVT) and at said second control pulse (LVT)
respectively when the corresponding step controlling signal (e.g., H1) is
absent and is present, the trailing edges of said duty cycle regulating
pulses being at the succeeding clock pulses, and
modulation logic means for deriving n trains of harmonic-reduced transistor
switching pulses (1a . . . na) each of which corresponds to one of said
reference waves and regulates said first transistor (e.g., 1A) in the
associated inverter phase leg (e.g., .phi..sub.1) and follows the
complement (e.g., VT1) of said train of duty cycle regulating pulses
during the positive half cycle of the corresponding reference wave (e.g.,
A) and follows said train (e.g., VT1) of duty cycle regulating pulses
during the negative half cycle of said corresponding reference wave, said
modulation logic means also deriving the complements (1b, . . . nb) of
said trains of transistor switching pulses which respectively control said
second transistors in the associated inverter phase legs. |
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Claims |
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Description |
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This invention relates to static electrical inverters and in particular to
transistor bridge inverter drives of the PWM type for driving an induction
motor.
BACKGROUND OF THE INVENTION
An a.c. motor does not require a commutator but is not generally regarded
as a variable speed machine because its speed is a function of its applied
frequency which is normally fixed. If variable frequency and variable
voltage power is connected to a commutatorless a.c. motor, it is possible
by control of the frequency and amplitude of the applied voltage to
provide an efficient variable speed drive. With full rated voltage applied
to the stator winding of an induction motor, its speed is nearly
proportional to the frequency of the applied voltage and is practically
independent of load. By controlling the frequency and amplitude of the
stator voltage in such a manner as to maintain constant flux in an
induction motor, it is possible to effect efficient variable speed
control. With the voltage-to-frequency ratio controlled so as to maintain
constant flux, the motor torque is determined by the slip frequency
between the applied stator frequency and the output shaft frequency
irrespective of motor speed.
The normal steady state operating range of an induction motor is over the
portion of the torque/slip characteristic which has a positive slope.
However, if the applied frequency and voltage can be controlled so as to
keep the absolute slip frequency less than the pullout slip frequency, the
machine can be made to operate on the most favorable portion of the
torque/slip characteristic under all conditions so it is possible to
realize the maximum driving torque of which the machine is capable at all
speeds.
Solid state variable frequency and variable voltage power supplies of the
cycloconverter type are used for variable speed control of induction
motors, but the upper output frequency limit of a cycloconverter is
usually less than that of the supply frequency, which places a practical
limitation on the range of application for cycloconverter drive systems.
Solid state variable frequency power supplies using an a.c. to d.c. SCR
converter followed by a variable frequency inverter are also known for
variable speed control of an induction motor, but such systems have
relatively low input power factor and relatively high percent of harmonics
in the motor current which results in high motor losses and in torque
oscillations.
D.c. to a.c. bridge inverter motor drives are known in which switching
devices such as transistors connected in a bridge circuit with a d.c.
source are selectively driven into conduction at a predetermined rate to
convert, or chop the d.c. into a square-wave a.c. output. In these
inverters it is customary to insert a filter after the inverter output
when a sinusoidal output is desired. The filter extracts the sinusoidal
fundamental component from the output which consists of fundamental plus
harmonics. The filtering problem is extremely difficult in variable
frequency power supplies since conventional filters have a fixed frequency
characteristic, and the inverter may have a 20 to 1 frequency range.
OBJECTS OF THE INVENTION
It is an object of the invention to provide an improved polyphase pulse
width modulation (PWM) inverter motor drive utilizing transistors to
derive a voltage of adjustable frequency and magnitude for driving a three
phase electrical motor.
It is a further object of the invention to provide such an improved PWM
transistor bridge inverter drive which is capable of driving a fully
loaded induction motor so that motor output torque is constant over a wide
speed range. A still further object is to provide such an improved PWM
bridge inverter drive for driving an a.c. motor which controls frequency
and amplitude of the motor stator voltage so as to maintain constant flux
in the motor and to keep the absolute slip frequency less than the pullout
frequency at all speeds. Another object is to provide such an improved PWM
transistor inverter drive which is adjustable to optimally drive the motor
for best performance, i.e., constant rated torque below motor base speed
and rated horsepower above base speed. A further object is to provide such
an improved PWM transistor inverter motor drive which can be adjusted so
that motor output torque is constant over the entire speed range.
A further object of the invention is to provide a transistor PWM bridge
inverter, variable frequency and variable voltage power supply for driving
a three phase motor which maintains constant flux in the motor over a wide
speed range and has improved means to reduce harmonics in the current
supplied to the motor.
Another object is to provide such a bridge inverter power supply which
maintains constant flux in the motor and reduces harmonics in the motor
currents and also provides low voltage-drop paths for reactive current
during the intervals between power pulses.
A still further object is to provide such a PWM transistor bridge inverter,
variable frequency and variable voltage power supply for driving a three
phase motor which prevents oscillation of the motor and also reduces
heating of the motor in comparison to prior art variable frequency static
power supplies.
Another object of the invention is to provide an improved PWM transistor
bridge inverter, variable frequency and variable voltage power supply for
driving an electrical motor which controls the voltage-to-frequency ratio
so as to maintain constant flux in the motor over a wide speed range and
wherein the transistor chopping frequency is substantially lower than the
clock pulse frequency which establishes the PWM pulse period.
Still another object is to provide such an improved transistor inverter
variable frequency and variable voltage power supply for driving an
induction motor wherein transistor chopping is minimized at the portion of
each half cycle of the fundamental wherein the transistors will conduct
peak current during machine loading.
A further object is to provide such an improved PWM transistor inverter,
variable frequency power supply for driving an induction motor which
reduces the number of switching operations that must occur to time ratio
control switch the output voltage of the inverter so as to maintain flux
constant in the motor and to neutralize harmonics in the motor current
while maintaining low voltage-drop paths for inductive current in between
applied voltage pulses.
SUMMARY OF THE INVENTION
A harmonic-reduced, variable frequency and variable voltage transistor
bridge inverter drive of the PWM chopper type controls frequency and
amplitude of stator voltage applied to an induction motor so as to
maintain constant flux in the motor and operate the motor on the most
favorable portion of its torque-slip characteristic under all conditions,
thereby permitting motor output torque to be constant over a wide speed
range. The motor drive includes a three phase bridge inverter with first
and second transistors in each phase of the bridge connected in series
across a d.c. source and also includes an oscillator for generating a
train of clock pulses when frequency is a function of the magnitude of an
analog speed signal. A resettable volt/hertz integrator senses the output
voltage of the inverter and derives a train of ramp pulses synchronized to
the clock pulses whose magnitude varies as a function of the integral of
the inverter output voltage with respect to time, and the ramp pulses are
compared to first and second reference voltages to derive phase-displaced
first and second control pulses. A three phase generator derives three
phase reference waves having periods which include a predetermined number
of clock pulses and which are associated with individual phases of the
bridge. The fundamental output voltage of individual phases of the bridge
are regulated in accordance with the three phase reference waves, and
pulse width modulating means switch transistors in respective phases of
the bridge by variable width pulses whose leading edges are established by
the clock pulses. The pulse width modulating means terminate PWM voltage
pulses conducted by the transistors in the respective bridge phases at the
first and at the second control pulses in such a manner that the bridge
inverter generates a wave form approximating a twelve-step output wave in
which fifth and seventh harmonics are substantially reduced. Only two
different width PWM pulses are required to accomplish a two-state
voltage-to-frequency ratio which maintains constant flux in the motor and
reduces harmonics in the current supplied to the motor.
In the preferred embodiment an interval generator derives three trains of
60.degree. width, step controlling pulses which span respective zero
crossings of the corresponding phase reference waves, and a volt-second
switch derives for each bridge inverter phase a train of duty cycle
regulating pulses whose leading edges are respectively at the first
control pulse when the step controlling pulse is absent and at the second
control pulse when the step controlling pulse is present and whose
trailing edges are at the succeeding clock pulse. Modulation logic means
generate trains of transistor switching pulses for switching the first and
second transistors in each bridge phase in opposition so that the first
transistor follows the complement of said duty cycle regulating pulses
during the positive half cycle of the corresponding phase reference wave
in order to apply power pulses to the motor and follows said duty cycle
regulating pulses during the negative half cycle of the corresponding
phase reference wave to provide paths for "free-wheeling" pulses, i.e.,
low voltage-drop paths for reactive current pulses in between the power
pulses.
DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of the invention will be more
readily apparent from the following detailed description when considered
in conjunction with the accompanying drawings wherein:
FIG. 1 is a block diagram of a variable frequency and variable voltage
power supply for a three phase a.c. motor embodying the invention;
FIG. 2a shows the output voltages from a conventional three phase bridge
inverter and FIG. 2b illustrates twelve-step approximate output voltages
from inverter INV shown in FIG. 1 and wherein harmonics are substantially
reduced in comparison to the waveforms of FIG. 2a (the reference wave A
not being shown to scale);
FIG. 3 illustrates typical reduced harmonic patterns of PWM pulses
generated by the transistor bridge inverter motor drive of FIG. 1 to
provide selectively variable frequency and variable voltage to the motor;
FIG. 4a shows the torque versus frequency characteristic of the motor when
optimally driven by the bridge inverter of FIG. 1 for best performance and
FIG. 4b shows different terminal voltage versus motor frequency
characteristics with which the bridge inverter power supply shown in FIG.
1 can drive the a.c. motor so that its output torque is constant over a
wide speed range;
FIGS. 5a through 5m illustrate pulses which are derived at different points
in the bridge inverter motor drive shown in FIG. 1;
FIG. 6 illustrates the voltage controlled oscillator of the FIG. 1 motor
drive and waveforms of signals generated therein;
FIG. 7 shows the resettable integrator and the first and second level
comparators of the FIG. 1 variable frequency power supply as well as
pulses generated therein;
FIG. 8 shows the divide-by-six counter of the FIG. 1 motor drive and the
trains of timing pulses generated thereby;
FIG. 9 shows the three phase generator of the FIG. 1 motor drive and the
three phase reference square waves generated thereby;
FIG. 10 illustrates the portion of the 60.degree. interval generator of the
FIG. 1 apparatus for phase one of the bridge inverter and the 60.degree.
width pulses generated thereby;
FIG. 11 shows the volt-second latch and the portion of the volt-second
switch of the FIG. 1 motor drive for phase one of the bridge inverter;
FIG. 12 shows the portion of the modulation logic for phase one of the
bridge inverter motor drive shown in FIG. 1; and
FIG. 13 shows a current path for free-wheeling pulses through two phases of
the bridge inverter and associated motor windings.
DETAILED DESCRIPTION
Referring to the schematic block diagram of FIG. 1, the PWM transistor
inverter motor drive of the invention supplies voltage of adjustable
frequency and adjustable magnitude to drive and control speed of a three
phase induction motor M having Y-connected phase windings W1, W2 and W3.
Power from a suitable alternating current supply such as a three phase,
220 volt source may be rectified in a full wave bridge rectifier BR to
provide unidirectional power of potential E such as 300 volts to a
twelve-step, six-element three phase transistor bridge inverter INV.
Bridge inverter INV has a pair of power transistors in each leg connected
in series between the 300 volts positive supply bus + and the zero voltage
reference bus -.
One leg of inverter bridge INV includes a pair of power transistors 1A and
1B with their collector-emitter paths connected in series between the 300
volt positive bus + and the zero voltage reference bus - and with the node
between transistors 1A and 1B consituting phase one output terminal
.phi..sub.1 connected to phase winding W1 of motor M. Transistors 1A and
1B have uncontrolled feedback, or clamping diodes 1AD and 1BD respectively
connected in parallel with them in a reverse polarity relationship to
provide a path for reactive load current and limit reverse voltages when
the power transistors are turned off.
Similarly, leg two of bridge inverter INV includes a pair of power
transistors 2A and 2B having their emitter-collector paths connected in
series across the positive bus + and zero reference bus - with the node
between the two transistors constituting phase two output terminal
.phi..sub.2 coupled to phase winding W2 of motor M. Feedback diodes 2AD
and 2BD respectively are connected in parallel reverse polarity
relationship with transistors 2A and 2B. In a similar manner leg three of
bridge inverter INV includes power transistors 3A and 3B having their
emitter-collector paths connected in series across the positive bus + and
reference bus - with the node between the transistors constituting phase
three output terminal .phi..sub.3 connected to phase winding W3 of motor
M. Power transistor 3A has a feedback diode 3AD connected in inverse
polarity shunt relation therewith, and power transistor 3B also has a
feedback diode 3BD connected in inverse polarity shunt relation therewith.
It will be noted that transistors 1A-3C are arranged in the three legs for
three phase inversion.
Each inverter bridge output terminal .phi..sub.1, .phi..sub.2 and
.phi..sub.3 can be selectively connected to either the positive bus +
through a respective transistor 1A, 2A, or 3A or to the zero reference bus
- through a respective transistor 1B, 2B, or 3B, and in operation the
transistors in a given leg are switched in opposition so that when one
transistor, such as 1A, is turned on the other, such as 1B, is turned off.
Such inverters are well known and their manner of operation may be found
in the Bedford and Hoft text Principles of Inverter Circuits.
GENERAL THEORY OF HARMONIC REDUCTION
Before describing the time ratio control which selectively regulates
turning of the six transistor 1A through 3C of bridge inverter INV on and
off, it may be useful to describe the underlying theoretical
considerations of the instant invention. A three phase bridge inverter
such as INV when controlled in the conventional manner will inherently
apply a six-step square wave such as shown in FIG. 2a across the terminals
of motor M. Power is applied to motor M when a transistor in one leg
coupled to the positive bus +, such as 1A, (see FIGS. 1 and 13) and a
diagonally opposed transistor in another leg connected to the zero
reference bus -, such as 2B, are turned on simultaneously so that a path
is completed from the positive bus + through 1A in series with winding W1,
winding W2, and transistor 2B to the reference bus -, thereby applying
line-to-line voltage to the motor M. The waveforms designated V.sub.1-0,
V.sub.2-0 and V.sub.3-0 represent respectively the voltage between the
corresponding phase output terminals .phi..sub.1, .phi..sub.2, .phi..sub.3
and the zero reference bus when the inverter is controlled in the
conventional manner, and the waveforms V.sub.1-2, V.sub.2-3, and V.sub.3-1
represent the respective line-to-line voltages between these inverter
output terminals. A line-to-reference bus voltage such as V.sub.1-0 is the
resultant of conduction by the transistors 1A and 1B of the corresponding
phase lege. The line-to-line voltage such as V.sub.1-2 shown in FIG. 2(a)
is derived from combining the corresponding pair of line-to-reference
voltage waveforms such as V.sub.1-0 and V.sub.2-0, observing proper
polarity, and alternates from positive to negative in the form of pulses
which extend for two periods of 120 electrical degrees. When the inverter
is operated in the conventional manner, the phase of the resultant
line-to-line voltage such as V.sub.1-2 is shifted relative to the phase of
the line-to-reference bus voltages V.sub.1-0 and V.sub.2-0. The
line-to-line voltages do not contain even or triplen harmonics but do
contain high percentages of the other odd harmonics such as the fifth,
seventh, and eleventh. The fundamental component of the line-to-line
voltage produces the motor torque, whereas the harmonics result in
undesired torque pulsations and motor heating and inverter heating.
The induction motor current produced by a nonsinusoidal voltage such as
rectangular wave V.sub.1-2 shown in FIG. 2a is very rich in harmonics
because the harmonics do not see the same motor impedance as the
fundamental. The fundamental voltage sees the rotor resistance r.sub.2
transformed by the slip s in the relationship r.sub.2 /s. The slip is a
number rarely exceeding 0.05. However, because they are nonsynchronous,
the harmonics see an impedance identical to a machine with a stalled motor
wherein slip approaches unity. This is particularly significant at lower
frequencies where the equivalent reactances are small. The fifth harmonic
in the line-to-line voltage waveform V.sub.1-2 shown in FIG. 2a is
approximately 21% of the fundamental and the seventh harmonic is
approximately 14% of the fundamental. Current harmonics at low motor
speeds are higher than this and contribute significantly to motor heating
and to torque pulsations.
If additional steps are added to the waveforms so that they approach closer
to being sinusoidal, the relative height and width of the steps can be
controlled to cancel harmonics. If transistors 1A through 3B are
controlled so that inverter INV generates the stepped line-to-reference
bus voltages such as V.sub.1-0 and V.sub.2-0 shown in FIG. 2b which when
added result in the twelve-step line-to-line voltages such as V.sub.1-2
the fifth and seventh harmon | | |
