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Claims  |
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What is claimed is:
1. The random access memory which comprises a monolithic semiconductor chip
having formed thereon:
a matrix of memory cells each including a data storage capacitor, the cells
being arrayed in rows and columns, the storage capacitor of each cell in
each column being connected to a corresponding column bus in response to a
voltage on a row address line and the data being transferred to and from
each cell in each column by the corresponding column bus;
a sense amp for each column bus for discriminating between at least two
voltage levels representative of logic states and storing the detected
logic state;
a plurality of address inputs;
row address latch means for storing address data applied to the address
inputs;
row decoder means for enabling a row address line designated by the address
data in the row address latch means;
a row address strobe signal input;
row address clock and control means responsive to a signal on the row
address strobe input for automatically causing the data on the address
inputs to be latched in the row address latch means, for causing a row
address line to enable the storage cells in the row, and for causing the
data in the storage cells to be transferred by the respective column buses
to the respective sense amp and stored, and for rewritting data from the
respective column buses into the respective cells;
a column address strobe signal input;
column address latch means for storing address data applied to said address
inputs;
a data bus;
column decoder means for enabling an addressed sense amp to transfer data
between the data bus and the enabled sense amp;
a data input;
a data input latch for storing data applied to the data input;
a data output;
a data output latch for storing at least two logic levels and applying
corresponding logic signals to the data output;
a chip select signal input;
a write signal input; and
column clock and control means responsive to a signal on the column address
strobe for latching data applied to the address line in the column address
latch means, and in the presence of a predetermined signal on the chip
select input for enabling an addressed sense amp to transfer data from the
sense amp through the data bus to the data output latch, and in the
presence of a predetermined signal on the chip select input and on the
write input for latching data applied to the data input in the data input
latch and transferring data from the data input latch to the enabled sense
amp while isolating the data output latch from the data bus.
2. The random access memory of claim 1 wherein each sense amp comprises:
a differential amplifier having reference and data input nodes, the
amplifier being adapted to output one logic signal when the inputs are
near the same voltage and another logic level when the inputs are at
different voltage levels, and means responsive to the row clock and
control means for precharging the respective column bus to a reference
voltage level and trapping the reference voltage on the reference input
node, and then outputting a logic level dependent upon the voltage level
of the respective column bus after the respective addressed memory cell is
enabled.
3. The random access memory which comprises a monolithic semiconductor chip
having formed thereon:
a matrix of storage cells arrayed in rows and columns, the storage cell in
each column being connected to a corresponding column bus in response to a
voltage on a row address line and the data being transferred to and from
each cell in each column by the corresponding column bus;
a sense amp for each column bus for detecting the logic state of an enabled
cell connected to the respective column bus as the cell is enabled and
holding the detected logic state;
row address means for enabling a row of storage cells designated by row
address data;
a row address strobe input for inputting a row address strobe signal to the
chip;
row address clock and control means responsive to a row address strobe
signal on the row address strobe input for automatically causing an
addressed row of storage cells to be enabled and the data in the storage
cells of the row to be detected by the respective sense amp and held;
a data bus;
column address means responsive to a column address strobe signal input to
the chip after the row address strobe signal for enabling an addressed
sense amp to transfer data between the data bus and the enabled sense amp;
and
data transfer means for transferring data between the data bus and
circuitry external to the chip.
4. In a random access memory which comprises a monolithic semiconductor
chip having a matrix of storage cells arrayed in rows and columns, the
method of addressing a storage cell which comprises applying a first set
of binary address signals to a number of address inputs to the chip and
then applying a second set of address signals to the same address inputs
to specifically identify a selected column of the array and thus identify
a selected cell.
5. The method of addressing a desired memory cell of a memory formed on a
monolithic semiconductor chip having a matrix of storage cells arrayed in
rows and columns which comprises sequentially applying first and second
sets of binary address signals to the same address inputs to the chip to
identify the row and column of the desired memory cell.
6. In a random access memory formed on a monolithic semiconductor chip and
having a series of precharge periods each followed by a data access period
initiated by a strobe signal, the method for outputting data from the chip
which comprises reading data from a selected memory cell during an access
period and storing the data read from the cell in a data output latch
during the remainder of the access period and at least a portion of the
succeeding precharge period, and outputting the data from the data output
latch to circuitry external of the chip during at least a portion of said
succeeding precharge period.
7. The circuit for producing a clock signal above a drain supply voltage
between first and second successive clock edges and substantially at a
source supply voltage after the second clock edge until a precharge signal
which occurs some period after the second clock edge and terminates before
the next first clock edge which comprises:
a precharge node,
an output node,
a capacitor coupling the precharge node and the output node,
a first transistor connecting the precharge node to the drain supply
voltage,
a second transistor connecting the precharge node to the source supply
voltage,
a third transistor connecting the output node to the drain supply voltage,
and
a fourth transistor connecting the output node to the source supply
voltage,
the second and third transistors being turned on by the precharge signal,
the first transistor being turned on by the first clock edge and the
fourth transistor being turned off by the second clock edge.
8. In a random access memory formed on a monolithic semiconductor chip and
having a plurality of memory cells each having a storage capacitor
connected to a column bus when a transistor is turned on by an enabling
signal, the method of detecting the logic level stored on the capacitor of
an enabled cell which comprises:
precharging the column bus to precharge voltage level,
sampling the precharge voltage level on the column bus and storing the
sampled voltage on a reference node,
then enabling a selected storage cell by turning the transistor of the
selected cell on,
detecting a predetermined change in the column bus from the sampled voltage
stored on the reference voltage, and
changing the voltage level on the column bus in the event a predetermined
change in the voltage level is detected, to a voltage level corresponding
to the voltage level of the capacitor of the enable cell before the cell
was enabled.
9. In a random access memory, the method of claim 8 wherein:
the column bus is precharged to a voltage near a drain supply voltage, and
the column bus is discharged to a voltage level near a source supply
voltage in the event a predetermined charge in the voltage of the column
bus is detected by turning a transistor on to connect the column bus to a
source supply voltage.
10. In a random access memory, the sense amp for detecting voltage levels
on a column bus connected to a memory cell by row enabling signal
comprising:
a differential amplifier having reference and data input nodes connectable
to the column bus, the amplifier being adapted to output, when enabled,
one logic state when the input nodes are near the same voltage level and
another logic state when the inputs are at different voltage levels, and
circuit means for precharging the column bus and the reference node to a
precharge level, then isolating the precharge node from the column bus and
connecting a memory cell to the column bus to change the voltage level of
the column bus if said other logic state is stored in the memory cell
without changing the voltage level on the reference node, and then
enabling the output of the amplifier.
11. In a random access memory formed on a monolithic chip and having a
plurality of memory cells arrayed in rows and columns, the method of
accessing data which comprises:
applying a row strobe to the chip to automatically transfer data from all
memory cells in an addressed row to a column register, and applying a
column strobe to the chip to automatically transfer data between an
addressed bit of the column register and circuitry external to the chip,
the row address data and column address data being substantially input to
the chip through the same address inputs to the chip.
12. In a random access memory which comprises a monolithic semiconductor
chip, the combination of:
a matrix of storage cells arrayed in rows and columns, the storage cell in
each column being connected to a corresponding column bus in response to a
voltage on a row address line and data being transferred to and from each
cell in each column by the corresponding column bus;
sense amp means for each column bus for discriminating between at least two
voltage levels representative of logic states and holding the detected
logic state;
a plurality of binary row address inputs to the chip sufficient in number
to binarily define the number of rows or columns, whichever is greater;
a row address strobe input for inputting a row address strobe to the chip;
row address decode means responsive to a row address strobe input to the
chip for decoding row address data and holding the addressed row of memory
cells enabled until termination of the row address cycle;
a column address strobe input for inputting a column address strobe signal
to the chip;
column address latch means for storing column address data applied to said
address inputs; and
column address decoder means responsive to a column address strobe signal
for enabling the transfer of data from the sense amp means for the column
identified by the column address.
13. In a random access memory which comprises a monolithic semiconductor
chip, the combination of:
a matrix of storage cells arrayed in rows and columns;
a plurality of address inputs limited in number to that required to define
the greater of the number of rows or columns for inputting a corresponding
number of address signals to the chip;
strobe input means for inputting time spaced row address strobe and column
address strobe signal to the chip;
row address means responsive to a row address strobe input through the
strobe input means for holding a row of storage cells defined by the
address signals then on the address inputs enabled for processing of data
therein; and
column address means responsive to a column address strobe input through
the strobe input means for holding the storage cells defined by the
address signals then on the address inputs enabled for processing of data
therein.
14. The combination of Claim 13 further characterized by means for
automatically in response to a row address strobe and independent of the
column address strobe refreshing data stored in all memory cells in the
row defined by the address signals then on the address inputs.
15. The method of addressing a selected memory cell of a matrix of memory
cells arrayed in rows and columns on a monolithic semiconductor chip
disposed in a multiple pin package which comprises:
applying one binary input of a set of binary inputs which identify the row
of selected memory cell to each of a set of address pins of the package;
applying one address strobe signal to a pin of the package to cause the row
address information on the set of address pins to be input and stored in
the circuit; then
applying each binary input of a set of binary inputs which identify the
column of the selected memory to one of the same set of address pins of
the package; and
applying another address strobe signal to a pin of the package to cause to
column address information on the set of address pins to be input to the
circuit.
16. In a memory formed on a monolithic semiconductor chip of a field effect
transistor and having a plurality of logic inputs to which logic input
signals are normally applied in sequence in the operation of the memory,
the input circuit comprising an inverter stage including:
an output node for the inverter stage;
a load impedance circuit including an impedance device and a first
transistor connecting the output node to a drain voltage supply node so as
to block any current through the impedance circuit when turned off; and
an input circuit including at least a second transistor connecting the
output node to a source supply voltage node, the gate of the second
transistor being a logic input to the chip;
the first transistor being turned on in response to a logic input signal
normally applied to another logic input to the chip before a logic signal
would normally be applied to the gate of the second transistor whereby the
inverter stage will be turned off and not dissipate energy in the absence
of the earlier logic signal.
17. In a random access memory formed on a monolithic semiconductor chip
having a matrix of memory cells and logic means for addressing a selected
memory cell of the matrix, the combination of
strobe input means for inputting an externally generated strobe signal to
the chip;
first means for applying externally generated alternative logic levels to
the chip for indicating that the chip is selected or not selected;
second means for applying externally generated alternative logic levels to
the chip for indicating a read cycle or a write cycle; and
logic means responsive to an externally generated strobe signal applied to
the strobe input means including data output latch means for:
a. in the presense of a chip not selected logic level on the first means
causing the data output to be an open circuit until responding to another
strobe input signal,
b. in the presence of a chip selected logic level on the first means and a
read cycle logic level on the second means producing a logic output
representative of the logic level stored in an addressed memory cell until
responding to another strobe input signal, and
c. in the presence of a chip selected logic level and a write logic level
automatically storing data in an addressed memory cell and a predetermined
state at the data output until responding to another strobe input signal.
18. In a random address memory formed on a monolithic chip and having a
matrix of memory cells arrayed in rows and columns, a set of address
inputs sufficient in number to logically define only the number of rows or
columns, whichever is greater, strobe input means for sequentially
inputting a row strobe signal and a column strobe signal to the chip, data
means for inputting and outputting binary data from the chip, and
read/write control input means for inputting a signal to the chip having a
read logic strobe for a read common and write logic strobe for a write
command, the method comprising:
applying a set row address signals representing a row of memory cells in
the matrix to the address inputs to the chip;
gating the row address signals into the chip in response to a row strobe
signal and then holding the row of memory cells identified by the row
address signals enabled;
applying a set of column address signals representing a column of memory
cells in the matrix to the same address inputs to the chip; and
gating the column address signals into the chip in response to a column
strobe signal to enable the processing of data in the memory cell of the
addressed row and the addressed column.
19. The method of claim 18 further comprising:
applying a succession of sets of column address signals to the address
inputs and a succession of column strobe signals to the strobe input means
while holding the same row of memory cells enabled to sequentially enable
the processing of data in a series of enabled memory cells in the
addressed row.
20. The method of claim 18 wherein the write logic state is applied to the
read/write control input means before said predetermined minimum time
after the column strobe signal of automatically causing the data output
from the chip to go to an open circuit and to automatically cause data at
a data input to the chip to be stored in the addressed memory cell.
21. The method of claim 18 further comprising:
applying said read logic state to the read/write control input means for a
predetermined minimum time before and after the column strobe signal for
automatically causing data in the addressed memory cell to be stored in a
data output latch and be output from the chip until after the next input
on the strobe input means.
22. The method of claim 21 further comprising changing the logic state
applied to the read/write control input means from the read logic state to
the write logic state after the predetermined minimum time after the
column strobe signal for automatically causing data to be input and stored
in the addressed memory cell while the data read from the addressed memory
cell continues to be stored in the data output latch.
23. In a random address memory formed on a monolithic chip and having a
plurality of memory cells arrayed in rows and columns, the method of
accessing data which comprises:
applying a row strobe signal to the chip to automatically transfer data
from all memory cells in an addressed row to a column register, and
applying a column strobe signal to the chip to then automatically transfer
data between an addressed bit of the column register and circuitry
external to the chip.
24. The method of claim 23 wherein a write signal is gated into the chip by
the column strobe signal to cause the automatic transfer of data at a data
input to the addressed memory cell.
25. The method of claim 24 wherein the data output is caused to go to a
predetermined logic state in the event a write signal is applied to the
chip before or within a predetermined time period after a column strobe
signal is applied to the chip.
26. The method of claim 23 wherein the absence of a write signal applied to
the chip at the time of the column strobe signal results in data from an
addressed bit of the column register being automatically output from the
chip in response to a column strobe signal.
27. The method of claim 26 wherein a write signal applied to the chip a
predetermined period of time after a column strobe signal is applied to
the chip automatically transfers data at a data input to an addressed
memory cell after data is output from the addressed bit of the column
register.
28. The method of claim 26 wherein the transfer of data to or from the chip
enabled by a chip select signal is disabled by the absence of a chip
select signal applied to the chip.
29. The method of claim 28 further characterized by causing:
the data output to go to an open circuit condition in the absence of a chip
select signal.
30. The method of claim 23 wherein a plurality of sets of addresses and
column strobes are sequentially applied to the chip after a single row
strobe to automatically sequentially transfer data between a plurality of
bits of the column register and circuitry external to the chip. |
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Claims |
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Description |
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The present invention relates generally to large scale integrated
semiconductor circuits, and more particularly relates to an integrated
circuit having a large number of binary storage cells which may be
randomly addressed for the purpose of reading data from, or writing data
into the address storage cell.
It is generally known that random access memories can be formed from a
large number of integrated semiconductor circuit chips each having a large
number of binary data storage cells. The largest circuits in wide spread
commercial use have heretofore had only 1,024 storage cells, each
comprised of a storage capacitor and three or more
metal-oxide-semiconductor field effect transistors (MOSFET) for storing
and reading the voltage on the storage capacitor. It has been proposed to
utilize dynamic storage cells in which only one transistor per storage
cell is used so that a larger number of such cells can be placed on a
single integrated circuit chip of practical size. The use of this type of
storage cell, however, makes the task of determining whether a logic "1"
or a logic "0" is stored in the cell very difficult because of the
relatively small change in voltage level resulting when the cell is
addressed. Another difficult problem resulting from an increase in the
number of cells is that a larger number of address inputs is required to
uniquely define a particular storage cell. The time required to retrieve a
particular bit of data from a random access memory, commonly referred to
as access time, is always a critical factor in such a system. Since a
large number of random access memory chips are typically used in a total
system with high packing densities, a high premium is placed on low power
consumption.
The present invention is concerned with an improved random access memory in
which 4,096 storage cells are arranged in sixty-four rows and sixty-four
columns. The chip has six address lines which go to the inputs of a six
bit row address latch and also to the inputs of a six bit column address
latch. Data applied to the six input lines indicating the row of a
particular storage cell is strobed into the row address latches by a row
address strobe signal. The row address strobe also initiates an automatic
cycle which then detects the logic level stored in each cell of the
addressed row and transfers the logic level to a corresponding bit of a
sixty-four bit storage register and also restores the cell to its initial
state. Address data is then applied to the six address inputs indicative
of the column of the particular storage cell, and a column address strobe
initiates a sequence which latches the address data in the column address
latch. If the chip is selected by a signal on a chip select input line,
the column address is decoded and the data in the addressed bit of the
sixty-four bit register which contains the data of the address cell is
then transferred to a data output latch. A write signal to the chip
strobes new data into a data input latch and automatically transfers the
new data into the addressed bit of the column register as well as into the
addressed cell of the storage matrix. On completion of the row address
strobe, the sixty-four storage cells in the addressed row have been
automatically refreshed with the data previously read from the cells
except as the addressed bit of the column register might have been
modified. Data on the output latch is valid between successive read
cycles. The write signal aborts the read cycle if it occurs prior to the
time data is to be transferred to the data output latch, in which case the
data output goes to a logic "1". In accordance with another important
aspect of the invention, the access time can be substantially reduced when
successively addressing storage cells in the same row because once a row
is addressed and data transferred to the column register, read, write or
read-modify-write cycles can be performed sequentially on any number of
bits in the column register merely by changing the address inputs for each
of a series of column address strobes. Since the general organization of
the random access memory requires only six address pins and a total of
only twelve data pins, the chip may be packaged in a standard sixteen pin
dual-inline IC package. Various aspects of the organization of the random
access memory as well as an improved sense amplifier circuit and other
specific circuits are hereafter pointed out with particularity in the
claims.
A more complete understanding of the invention may be had by referring to
the following detailed description of a preferred embodiment when taken in
conjunction with the drawings, wherein:
FIG. 1 is a schematic block diagram of a dynamic random access memory in
accordance with the present invention;
FIG. 2 is a schematic circuit diagram of one of sixty-four sense amp and
write circuits of the random access memory of FIG. 1;
FIG. 3 is a schematic block diagram of the row clock and control circuit of
the random access memory of FIG. 1;
FIG. 4 is a timing diagram which serves to illustrate the operation of the
row clock and control circuit of FIG. 3;
FIG. 5 is a schematic block diagram of the column clock and control circuit
of the random access memory of FIG. 1;
FIG. 6 is a timing diagram which serves to illustrate the operation of the
column clock and control circuit of FIG. 5;
FIG. 7 is a schematic circuit diagram of a typical delay stage used in the
clock and control circuits of FIGS. 3 and 5;
FIG. 8 is a timing diagram which serves to illustrate the operation of the
delay stage of FIG. 7;
FIG. 9 is a schematic circuit diagram of a typical input latch used in the
random access memory of FIG. 1;
FIG. 10 is a schematic circuit diagram of a decoder used in both the row
and column decode circuits of the random access memory of FIG. 1;
FIG. 11 is a schematic circuit diagram illustrating the data output latch
of the circuit of FIG. 1;
FIG. 12 is a schematic circuit diagram illustrating a NOR gate of the
circuit of FIG. 1;
FIG. 13 is a timing diagram which illustrates a typical read-modify-write
cycle of the circuit of FIG. 1; and
FIG. 14 is a schematic timing diagram which serves to illustrate the "Page"
mode of operation of the circuit of FIG. 1.
The following specification is divided into two major parts. The first part
describes the circuit components in detail without attempting to explain
the operation. The second part explains the operation while assuming that
the reader is familiar with the first part.
Referring now to the drawings, a dynamic random access memory in accordance
with the present invention is indicated generally by the reference numeral
10 in FIG. 1. The dynamic random access memory 10 is fabricated as a
single integrated circuit using MISFET (metal-insulator-semiconductor
field effect transistor) technology. The memory 10 is an N-channel system,
although a P-channel system could be used if desired. Accordingly as used
herein, "high" refers to V.sub.gg, whether positive for N-channel systems
or negative for P-channel systems, and low refers to ground potential.
The integrated circuit 10 preferably has a total of 4,096 binary storage
cells arrayed in a 64 .times. 64 matrix with rows R.sub.1 - R.sub.64 and
columns C.sub.1 - C.sub.64. Each storage cell, for example cell R.sub.1
C.sub.1, is comprised of a field effect transistor 11 and a capacitor 12.
The gate of transistor 11, and the gates of the transistors of all other
storage cells in the first row are connected to a row address line
RA.sub.1. Row address lines RA.sub.2 - RA.sub.64 are similarly connected
to the gates of all the transistors of the cells in rows 2 - 64,
respectively. Transistor 11 and capacitor 12 are connected between column
bus CB.sub.1 and a fixed potential which may be V.sub.gg or in this case
ground, as are the transistors and capacitors of all other storage cells
in the first column. The transistors and capacitors of the cells in
columns 2 - 64 are similarly connected to column buses CB.sub.2 -
CB.sub.64, respectively.
It will be appreciated that twelve binary bits are required to individually
address 4,096 storage cells. However, only six common address inputs are
continuously applied to a six bit row address latch 14 and to a six bit
column address latch 16. As will hereafter be described, six bit row and
six bit column address information is multiplexed into the row and column
address latches. A row address decoder 18 selects one of the row address
lines RA.sub.1 - RA.sub.64 in response to the six bits of data stored in
the row address latch. The sixty-four column buses CB.sub.1 - CB.sub.64
are connected to sixty-four sense amp and write circuits SA.sub.1 -
SA.sub.64, respectively, which form a sixty-four bit register as will
hereafter be described. One of the sixty-four sense amps is selected by
the column decoder 20 in response to a particular six bit address code
stored in the column address latch 16.
The row address latch 14, the row address decoder 18 and the row read and
refresh cycles of sense amps SA.sub.1 - SA.sub.64 are automatically
operated in a predetermined manner, which will presently be described, by
a row clock and control circuit 22 in response to a row address strobe.
The column address latch 16, the column decoder 20, the column read and
write cycles of sense amp and write circuits SA.sub.1 - SA.sub.64, and the
data output latch and buffer 28 are automatically operated by a column
clock and control circuit 24 in response to a column address strobe.
Data is input to a data input latch and buffer 26 which is controlled by
the column clock and control circuit 24 and the WRITE input as will
presently be described. A write command signal is applied together with
the column address strobe to a NOR gate 30, and a chip select signal is
applied to a chip select input latch 32. Four voltage inputs V.sub.bb,
V.sub.gg, V.sub.cc, and GND are required to operate the circuit, and are
indicated collectively by the reference numeral 34. Thus, it is important
to note that only a total of sixteen external connections are required to
operate the integrated circuit 10 which can thus be placed in a standard
sixteen pin package.
Each of the sense amp and write circuits SA.sub.1 - SA.sub.64 includes the
circuitry illustrated in the dotted outline in FIG. 2 and designated by
the reference characters SA.sub.1. Each sense amp is controlled by a
number of signals from the row clock and control circuit 22, which are
arranged along the top of FIG. 2, and by signals from the column clock and
control circuit 24, the data input latch 26, and the column decoder 20,
which are arranged along the right-hand edge of FIG. 2. It should be noted
that for convenience the control lines to the sense amplifiers and write
circuits SA.sub.1, SA.sub.2 and SA.sub.64 in FIG. 1 are arranged in the
same order as would be the case if the circuit shown in FIG. 2 were
rotated 90.degree. counterclockwise.
The sense amp SA.sub.1, for example, is comprised of transistors Q.sub.1
and Q.sub.2, Q.sub.3 and Q.sub.4, and Q.sub.5 and Q.sub.6, which are
connected between the column bus CB.sub.1 and a race initiate terminal 50.
Capacitive nodes 52, 54 and 56 are thus formed between transistors Q.sub.1
and Q.sub.2, Q.sub.3 and Q.sub.4, and Q.sub.5 and Q.sub.6, respectively,
which have small storage capacitance as represented by capacitors 62, 64,
and 66. The gates of transistors Q.sub.3 and Q.sub.5 are connected to the
reference enable line 58 and the gate of transistor Q.sub.1 is connected
to the signal enable line 60. The gate of transistor Q.sub.4 is controlled
by node 52, and the gate of transistor Q.sub.2 is controlled by node 54.
The relative sizes of transistors Q.sub.2 and Q.sub.4 and/or the size of
capacitors 62 and 64 are selected such that if nodes 52 and 54 are at the
same voltage when race initiate line 50 is switched from near V.sub.gg to
ground, as will hereafter be described in greater detail, node 54 will
discharge at a faster rate to ensure that transistor Q.sub.2 is switched
off and that transistor Q.sub.4 remains on. Conversely, if node 52 is at
predetermined voltage lower than node 54, when the race initiate line 50
is switched from near V.sub.gg to ground, transistor Q.sub.2 will remain
on and transistor Q.sub.4 will be switched off. It will be noted that node
52 also controls the gate of transistor Q.sub.6. Thus, if node 52 remains
high, node 56 follows node 50 to ground. Conversely, if node 52 follows
node 50 to ground, node 56 remains near V.sub.gg. Node 56 is connected to
the gate of transistor Q.sub.7 which connects the restore node 70 to the
gate of transistor Q.sub.8. A bootstrap capacitor 72 connects node 74 to
node 56 and operates in a bootstrap manner to keep transistor Q.sub.7 full
on in response to the restore node 70 going to a high voltage when node 56
is high.
Transistor Q.sub.9 connects column bus CB.sub.1 to the voltage supply
V.sub.gg to precharge the column bus to V.sub.gg less one threshold during
the precharge cycle. The gate of transistor Q.sub.9 is controlled by the
delay row precharge line 76. Transistor Q.sub.10 connects the column bus
CB.sub.1 to the data bus and is controlled by the column select input line
80. The column select input line 80 also is connected to the gate of
transistor Q.sub.11 to enable the write command which is then connected to
the gates of transistors Q.sub.12 and Q.sub.13 of the select sense amp
only. Transistor Q.sub.12 connects the complement data input line 82 to
node 74, and transistor Q.sub.13 discharges node 56 to ground when turned
on. Transistor Q.sub.14 is turned on by delayed column precharge 86 to
bring node 87 to the grounded potential of write command node 80 during
precharge time.
The row clock and control circuit 22 is shown in detail in FIG. 3. A row
address strobe clock input RAS is applied to an external pin 21 and then
to an inverter 100. The output of the inverter 100 is fed to a cascade of
eight delay stages 101 - 108. The output from inverter 100 is also applied
to the input of an inverter 110, the output of which is applied to delay
stage 112. The output of inverter 110 is applied to the precharge inputs
of delay stages 101 - 108, and to the input of a delay stage 112. The
output of inverter 100 is also applied to the precharge input of delay
stage 112.
Each of the delay stages is illustrated by the schematic circuit diagram of
FIG. 7. The delay stage 101, for example, is of the type described and
claimed in co-pending U.S. application Ser. No. 337,132, entitled "Low
Power, High Speed, High Output Voltage FET Delay-Inverter Stage", which
was filed on March 1, 1973, and the assignee of the present invention. The
delay stage 101 includes a bootstrap circuit comprised of transistors 120
and 121 connected in series between V.sub.gg and ground and forming an
output node D. A transistor 123 connects V.sub.gg to the gate of
transistor 120, which is indicated as node C. Capacitor 124 couples the
output node D to node C. A timing input node 125 is connected directly to
the gate of transistor 123 and to the input of a first timing stage
comprised of transistors 126 and 127 connected between V.sub.gg and
ground, the output of which is designated as node A. Node A is coupled to
the input of a second timing stage comprised of transistor 128 and 129
connected between V.sub.gg and ground, which has an output node B. Node B
is connected to the gate of transistor 121. Transistor 130 connects node C
to ground. A precharge signal is applied to the gate of transistors 127,
128 and 130, which are referred to as node R because the precharge signal
"resets" the stage.
The operation of the delay stage of FIG. 7 is illustrated by the timing
diagram of FIG. 8 where the curves represent the voltage on the nodes
designated by the same reference characters as the curves followed by the
subscribt "v". For example, assume that the input 125 is low, i.e., at
ground, and the precharge node R is high, i.e., at V.sub.gg. Transistors
127, 128 and 130 would then be turned on causing nodes A and C to be at
ground potential and node B to be one threshold below V.sub.gg which would
turn transistor 121 on, holding the output node D at ground. Then before
the input node 125 is brought high, the reset node R goes low as
illustrated in FIG. 8. As a result, transistors 127, 128, and 130 are all
turned off and transistor 123 turns on, thus charging node C toward
V.sub.gg, node B remaining high at this time. At the same time, node A
goes high as transistor 126 turns on, causing transistor 129 to turn on
and node B to now go toward ground, thus turning transistor 121 off a
predetermined time interval later after node C has been substantially
charged to V.sub.gg less one threshold while node D remains near ground.
As transistor 121 turns off, output D begins to go high, which bootstraps
node C above V.sub.gg as a result of capacitor 124, thus maintaining
transistor 120 full on and allowing output node D to very rapidly go all
the way to V.sub.gg. When the precharge node R again goes high, nodes A, C
and D go low and node B goes high.
The row clock signals A.sub.R - J.sub.R in FIG. 4 are representations of
the voltages produced by inverter 100 and delay stages 101 - 108,
respectively, in response to the row address strobe RAS. The outputs of
these components are designated by the same reference characters as the
clock signals. In addition, the output of inverter 110 is indicated as the
First Row Precharge (FRP) in FIG. 4 which is essentially the same as the
row address strobe except at the higher level of V.sub.gg, typically
twelve volts, V.sub.gg rather than TTL voltage levels, typically less than
three volts. The output of delay stage 112 is designated as the Delayed
Row Precharge (DPR). The DPR signal goes from V.sub.gg to ground with the
row address strobe RAS because delay stage 112 is reset by clock output
A.sub.R. The delayed row precharge DPR goes high one delay interval after
the first row precharge goes high as illustrated in FIG. 4.
Referring once again to FIG. 3, clock output A.sub.R from inverter 100 and
clock output B.sub.R from delay stage 101 are applied to the row address
latch 14. The row address latch 14 is comprised of six bits, one of which
is indicated generally by the reference numeral 14a in FIG. 9. The latch
14a is of the type described and claimed in co-pending U.S. application
Ser. No. 441,500, entitled "Dynamic Data Input Latch and Decoder", filed
Feb. 11, 1974, and assigned to the assignee of the present application.
The latch 14a is comprised of cross coupled transistors 150, 151, 152, and
153. Transistors 150 and 151 are connected between an enable node 154 and
ground, and transistors 152 and 153 are also connected between the enable
node 154 and ground. The gates of transistors 150 and 153 are
interconnected as are gates of transistors 152 and 151. Transistors 150
and 153 have a relatively low transconductance for a given source-to-gate
voltage when compared to those of transistors 152 and 151. A true output
node 156 is formed between transistors 150 and 151, and is coupled to gate
node 164 by capacitor 157, and a complement output node 158 is formed
between transistors 152 and 153, and is coupled to node 160 by capacitor
159. The gate node 160 of transistors 152 and 151 may be precharged to
V.sub.gg less one threshold through transistor 162, while gate node 164 of
transistors 150 and 153 may be precharged through transistor 166. The
gates of transistors 162 and 166 are controlled by a precharge node 176.
Node 160 is connected to ground by transistors 168 and 170 in series, the
gate of 168 being the data input node, and the gate of transistor 170
being connected to the strobe node 172. Node 164 is connected to ground by
transistor 174, the gate of which is connected to the complement output
node 158.
When the precharge signal to node 176 goes to V.sub.gg, nodes 160 and 164
are precharged to V.sub.gg less one threshold. Both the enable node 154
and the strobe node 172 are low so that transistor 170 and 174 are turned
off. Transistor 168 is turned on by a logic "1" input or off by a logic
"0" input. Assume that the data input is a logic "1". When the precharge
input goes low, transistors 162 and 166 are turned off, trapping the
precharge voltage on nodes 160 and 164. The strobe node 172 is first
brought high which turns transistor 170 on, then the enable node 154.
Since is was assumed that data input transistor 168 was turned on by a
logic "1" input, a conductive path from node 160 to ground is established.
Node 160 is then discharged to ground before the enable signal occurs.
When the enable does occur, transistors 150 and 153 are on while
transistors 151 and 152 are off. With transistor 150 on and 151 off, the
true output, node 156, follows the enable signal, node 154, all the way to
V.sub.gg since bootstrap capacitor 157 maintains the gate drive on
transistor 150 during the switching transient. Furthermore, with
transistor 152 off and 153 on, the complement output, node 158, remains at
ground.
Assume now that the data input is at a logic "0". In this case no
conductive path is formed between node 160 and ground. Both nodes 160 and
164 are at the same high voltage when the enable signal occurs, so
transistors 150, 151, 152 and 153 are all conductive. Since the
transconductance of transistors 151 and 152 are greater than those of 150
and 153, node 158 rises at a faster rate than does node 156, typically
twice as fast. Node 158 reaches transistor threshold voltage while node
156 is still well below threshold. When threshold is reached on node 158,
transistor 174 becomes conductive, discharging node 164. With node 164
discharged, transistors 150 and 153 are turned off. With 151 turned on and
150 turned off, the true output, node 156 returns to ground without ever
reaching threshold voltage. In the meantime, transistor 153 is off and 152
is conductive so that the complement output, node 158, follows the enable
signal all the way to V.sub.gg since the turn on voltage of transistor 152
is maintained by bootstrap capacitor 159.
Thus, in the event of an input "0" the complement output follows the enable
signal to V.sub.gg with the true output remaining essentially at ground
while with a logic | | |
