A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a delay by the second delay circuit, whereby the output signal is made apparently free from the delays due to the preceding stage or stages and to the memory and logical circuits.
In a digital system including a digital computing module which generates a repeating sequential series of first pulses and a group of second pulses simultaneously with each of first pulses for energizing a dynamic numerical display device and to which key input information is coupled as timing pulses, during a first period of a predetermined time interval the display device is driven by the first and second pulses while during a second period of the predetermined time interval the display device is not driven but the timing pulses are coupled to the computing module.
A liquid crystal display element-driving circuit wherein output signals from a decoder for decoding coded time data are supplied to a plurality of exclusive OR gates through the corresponding NAND gates; an output signal from a liquid crystal driving pulse generator is sent forth in common to the exclusive OR gates, and outputs from the respective exclusive OR gates are conducted to the corresponding segment electrodes of the liquid crystal display element, and which further comprises first and second logical level voltage-generating circuits; switch circuits controlled by said first and second logical level voltage-generating circuits, whereby all the segment electrodes can be impressed with voltage having the same logical level by means of said first and second logical level voltage-generating circuits and corresponding switch circuits.
A method and apparatus is provided for efficiently and automatically removing unwanted temporal lighting variations from image sequences. Specifically, temporal light variations from a sequence of images are removed by a process of selecting a reference image (R) and designating a portion of the reference image as a reference image region (M), designating a first portion of at least one base image (F) of the sequence of images as a first selected image region (M') and a second portion as a second selected image region (M"), generating a color mapping by comparing the selected image region of the base image (M') with the reference image region of the reference image frame (M), and applying the color mapping to the second selected image region (M") of the base image (F) to generated a corrected image (F'). Three separate methods of performing the color mapping are disclosed.
