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BACKGROUND OF THE INVENTION
Prior art electronic time-keeping devices, whether wristwatch, wall-mount
or table-top clocks, have employed frequency divider methods of
time-keeping, wherein the output signal of a stable crystal oscillator is
repetitively divided to an appropriate lower frequency and applied to
switching, logic and decoding circuits for display to the user as
real-time. The calendar date is included in some of these devices such as
the one described in U.S. Pat. No. 3,803,834. The same basic circuitry is
also used to construct electronic stopwatches.
Frequency divider circuits require as many data lines and decoders as there
are dividers to display the data. Thus there is no single data line from
which time data can be accessed. Furthermore, for alarm circuits, a
plurality of comparators are required. Because of the multiplicity of
lines from which the time data must be accessed and the commensurate
amount of additional circuitry required use of the data for other purposes
such as real-time speed and distance calculations is more difficult.
SUMMARY OF THE INVENTION
The present invention comprises five circulating shift registers (CSR's),
time base and controller circuits and display. Time data for real-time,
split times (i.e. time intervals measured by stopwatches) and calendar
dates circulates in serial format in a separate CSR for each of the
above-named time units. The data is available via a single access line
from each CSR. Since the data is in serial form, only one comparator is
required for the alarm register.
The real-time, stopwatch and calendar date CSR's have a binary adder, adder
controller and auxiliary register coupled to 32 serially-connected,
clocked delay elements. The auxiliary register includes three delay
elements, also clocked and serially connected. The alarm CSR includes a
comparator coupled to 32 serially-connected and clocked delay elements.
Original time data for setting the real-time and date register is entered
via the display register. Time data from the CSR's for display is
transmitted to the display via the display register. The time base and
controller comprise logic gates and flip-flops which provide timing and
command signal respectively, to the five CSR's and the display means.
Real-time data is available for 8 digits of display, 1 digit each for
hundredths-of-seconds (.01 seconds), tenths-of-seconds (0.1 seconds),
seconds (1.0 seconds), tens-of-seconds (10 seconds), minutes (1.0
minutes), tens-of-minutes (10 minutes), hours (1.0 hours) and
tens-of-hours (10 hours). Splits may be displayed as described for
real-time data or as 6 digits of seconds units and 1 digit of
hundredths-of-seconds and 1 digit of tenths-of-seconds. Calendar dates
comprise a 6 digit display, 2 digits each for day of the months, month of
the year and year of the century without century designation. A seventh
digit is used for numerically indicating the day of the week relative to a
first day assignable by the user.
The 8-digit display comprises 32 bits of time data, each digit comprising a
4-bit data word. When the value of the data word in the auxiliary register
is 10, and that data word represents the 0.01, 0.1, 1.0 seconds, the 1.0
minutes or the 1.0 hours digits, a one is carried to the 0.1, 1.0, 10
seconds, the 10 minutes or the 10 hours digits, respectively. The carry is
performed by the adder controller according to conventional rules of
addition. However, a one must be carried when the 10 seconds and 10
minutes digits reach a value of 6. The mode setting determines when a one
must be carried from the 1.0 hour digit to the 10 hour digit, and when the
10 hour digit is reset to zero upon reaching a value of 2 or 3.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an electronic time-keeping circuit according
to the preferred embodiment of the present invention.
FIGS. 2A and 2B is a logic diagram of an electronic calculator interface
circuit and the controller of the time-keeping circuit of FIG. 1.
FIGS. 3A and 3B is a logic diagram of the time base of the timekeeping
circuit of FIG. 1.
FIG. 3C is a diagram of the timed command signals provided by the timing
circuit of FIG. 3.
FIG. 4 is a logic diagram of the real-time register of the time-keeping
circuit of FIG. 1.
FIG. 5 is a logic diagram of the stopwatch register of the time-keeping
circuit of FIG. 1.
FIG. 6 is a logic diagram of the alarm register of the time-keeping circuit
of FIG. 1.
FIG. 7 is a logic diagram of the calendar date register of the time-keeping
circuit of FIG. 1.
FIG. 8 is a logic diagram of the display register of the time-keeping
circuit of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, CSR's 40, 50, 60 and 70 receive timing and command
signals from time base 30, and controller 20, respectively. Real-time
register 40 and date register 70 receive original time data for setting
these CSR's to the correct time and date, and all CSR's output time data
for display to the user via display register 80.
FIGS. 2A and 2B shows one embodiment of controller 20. Any embodiment which
provides the command signals defined by the logic equations given in Table
I is adequate to control the time-keeping circuit of the present
invention. The preferred embodiment of this invention is capable of
stand-alone operation or operation in combination with an electronic
calculator. FIGS. 2A and 2B also includes one embodiment of an interface
to the calculator with which the time-keeping circuit of the present
invention is designed to work. Any interface circuit can be used so long
as appropriate signals are provided to ff's DREAD, TRN, DR1, DR2, DR3 and
DR4 of controller 20 to enable it to provide the command signals defined
in Table I.
Table I
__________________________________________________________________________
Controller Logic Equations
__________________________________________________________________________
IS = ISCA+SYNC+DELAY
LX1 = IS1.DS+DS.CS
JXIS = LX1.ZJS+YIS+CS.ZIS
KXIS = 1
JYIS = ZIS.LX1+XIS+ZIS.IS1.DS.CS.BS
KYIS = XIS+TITE7
JZIS = XIS+YIS+DS.CS.BS
KZIS = YIS.KYIS+YIS.LX1
CLXYZ = SYNCA.XK1.XK4.PHASETWO+XK2.XK3.ZIS+ZIS XK2
CLIS = SYNC+PHASETWO+XIS.YIS
SETMD = DS+CS+YIS.ZIS.XIS+PHASETWO
MODE = YIS.ZIS.XIS+DS+CS
DREAD = YIS.ZIS.XIS+CS
DELAY = XIS.YIS.ZIS
JTRN = READ.DR3
KTRN = TITE0
CLTRN = SLOCK
DHMS = DR1
CLHMS = MODE+DR3+DR2
DH24 = DR1
CLH24 = MODE+DR3+DR2
DCOM1 = DR1
DCOM2 = DR2
CLCOML
= MODE+DR3
SEAD = READ.SLOCK
T1TC = COM1+COM2
T2TC = COM1+COM2
T4TC = COM1+COM2
F1T1 = TRN.DR1.DR2
F5T1 = F1T1
F2T2 = TRN.DR1.DR2
F5T2 = F2T2
F3T3 = TRN.DR1.DR2+FIT3
F5T3 = F3T3+FIT3
F4T4 = TRN.DR1.DR2
F4T5 = F4T4
F1T5 = SEAD+DR1+DR2
F2T5 = SEAD+DR1+DR2
F3T5 = SEAD+DR1+DR2
F4T5 = SEAD+DR1+DR2
F5T5 = F5TE = TRN+SEAD
FET5 = SEAD+TRN
FIT5 = F5TO = TRN+DR4
__________________________________________________________________________
DELAY ELEMENTS
IS1 CLOCKED BY PHASE TWO
SYNCA CLOCKED BY PHASE TWO
DS, CS, BS CLOCKED BY CLIS
DR1, DR2, DR3, DR4 CLOCKED BY SETMD
D FLIP-FLOPS
HMS CLOCKED BY CLHMS
H24 CLOCKED BY CLH24
COM1 CLOCKED BY CLCOM1
COM2 CLOCKED BY CLCOM1
JK FLIP-FLOPS
TRN CLOCKED BY SLOCK
XIS, YIS, ZIS CLOCKED BY CLXYZ
Referring to FIGS. 3A and 3B the circuit shown includes time base 30 for
the preferred embodiment of the present invention, wherein an accurate and
stable 3.2 KHz oscillatory signal, hereinafter referred to as SLOCK, is
applied to frequency divider flip-flops 301, 302, 303, 304 and 305. SLOCK
is also the clock pulse used to clock the delay elements of the CSR's. The
time base provides timing signals to the registers and calculator
interface circuit which are developed by the frequency divider flip-flops.
The timing signals, defined by the logic equations given in Table II, are
then transmitted to the registers after processing by logic elements 306
through 319. FIG. 3C shows these timing signals relative to one another
and to the units of time they affect. Flow of time data and timing signals
in the CSR's will be more fully described in connection with the
description of the real-time register.
Table II
__________________________________________________________________________
Time Base Logic Equations
__________________________________________________________________________
ECLOCK
= READ.PHASETWO.XK3.XK5.XK6+XK3.XK4.XK6.SLOCK
ACLOCK
= SLOCK
BCLOCK
= SLOCK
CCLOCK
= SLOCK
DCLOCK
= SLOCK
TM4 = XT1+XT2
TE6 = XT3+XT4+XT5
TE7 = XT3+XT4+XT5
TL6 = XT3+XT4.XT5
TE2 = XT3+XT4+XT5
TE0 = XT3+XT4+XT5
TE1 = XT5+XT4+XT3
TE3 = XT5+XT4+XT3
TCOM = TE0.TM4+TM4.XT5+XT5.XT3+XT5.XT4
JK FLIP-FLOP:
XT1 CLOCKED BY SLOCK
XT2 CLOCKED BY XT1
XT3 CLOCKED BY ST2
XT4 CLOCKED BY XT3
XT5 CLOCKED BY XT4
__________________________________________________________________________
Referring to FIG. 4, real time register 40 comprises delay elements A1
through A32, binary adder 41, adder controller 43 and auxiliary register
45. Delay elements A1 through A32 may be conventional, clocked flip-flops
(ff's) or the same or similar to those described in U.S. Pat. application
Ser. No. 468,958 entitled "A Circulating Shift Register Memory Having
Editing and Subroutining Capability", filed May 10, 1974 by Chung C. Tung
and which is assigned to the assignee hereof. Binary adder 41 includes a
plurality of AND gates, NOR gates and inverters connected as shown to
accept time data from delay elements A29 through A32 and to combine that
data with data from adder controller 43 via data lines 42 and 44. Adder
controller 43 also includes AND gates, NOR gates and inverters in addition
to NAND gates and ff 430, connected as shown to accept timing and command
signals from time base 30 and controller 20, respectively, and to monitor
the output of and to provide carry data to, binary adder 41. Adder
controller 43 also provides information to auxiliary register 45 for
further processing of each digit code after processing thereof by binary
adder 41. Auxiliary register 45 includes three delay elements 450, 451,
452 AND, NAND, and NOR gates and inverters connected as shown to provide
intermediate storage of 3 bits of each digit of time data as it circulates
in the CSR. Operation of auxiliary register 45 is described more fully
below.
In operation, real-time data circulates in serially connected delay
elements A1 through A32 at a 3.2 KHz rate, i.e., one circulation every
0.01 second. With every complete circulation of the CSR, the data word
representing the 0.01 second digit is incremented by binary adder 41 when
the 4 bits of that data word are transferred from delay elements A29
through A32 to AX1, AX2, AX3, and A1, respectively. It should be noted
that the rate at which the time data is incremented may be selected to
suit the frequency of circulation in the CSR.
The operation of binary adder 41 will be described with reference to FIGS.
3a and 4 and in terms of positive logic signal convention. Assuming the
data word representing the 0.01 second digit is zero, a zero appears at
the Q output of delay elements A29 through A32. During each positive pulse
in timing signal TM4, the Q output of carry flip-flop 430 is a one, the
output of gate 410 is a zero. Since the Q output of ff 430 is a zero and
the Q output of A32 is a one, the output of gate 411 is also a zero. Since
both inputs of gate 412 are zero, the output thereof, which is the first
bit of the 4-bit data word representing the 0.01 seconds digit is now a
one. That bit is then transmitted to A1 via gates 453, 454 and 455 and
inverting amplifier 456. Recalling that a zero appears at the Q output of
A31, a zero appears at the output of gate 415 since the output of gate 413
is also a zero. The output of gate 413 is a zero because the Q output of
A32 is a one and the Q output of ff 430 is a zero. Since the Q output of
A31 is a one and the output of inverting amplifier 414 is a one, the
output of gate 416 is also a one. Thus, the output of gate 417 is a zero
since the inputs thereof are not alike.
The outputs of gates 422 and 427 are also zero by similar analysis. Since
the Q output of A30 and the output of gate 418 are zero, the output of
gate 420 is also a zero. Conversely, the output of gate 421 is a one
because the Q output of A30 and the output of inverting amplifier 419 are
also a one. Therefore the output of gate 422 is a zero since the inputs
thereof are not alike. Similarly, since the Q output of A29 and the output
of gate 423 are both zero, the output of gate 425 is a zero, and the
output of gate 426 is a one because the Q output of A29 and of output
inverting amplifier 424 are also one. Hence, the output of gate 427 is a
zero.
No carry to the next 4-bit data word is generated until the data word
representing the 0.01 digit is incremented to a binary value of ten, which
is 1010 in binary format. Until then, the binary value of that data word
continues to increment in the manner just described. However, when 1, 0, 1
and 0 appear at the outputs of gates 427, 422, 417 and 412, respectively,
(hereinafter referred to as the output of binary adder 41) at TM4, carry
ff 430 is preset by adder controller 43 to increment the 0.1 seconds digit
as follows: the output of detector gate 431 is a one since both inputs are
also ones; since the output of gate 432 is a zero when any one of the
inputs thereof is a one, the output of gate 433 is a one because the
inputs thereof are not alike at TM4; the output of gate 434 is a zero
because the one output of gate 433 is applied to one input at the same
time TE7 is applied to the other input; and the output of gate 435 is a
one since the output of gate 436 is a zero if and only if both inputs are
ones.
When the binary word representing the 0.1 and 1.0 seconds, the 1.0 minutes
and the 1.0 hours digits reaches a value of ten, carry ff 430 is preset to
increment the 1.0 and 10 seconds, 10 minutes and 10 hours digit,
respectively, in substantially the same manner as that described above for
incrementing the data word representing the 0.1 seconds digit. When the
binary data word representing the 10 seconds and the 10 minutes digits
reaches a value of six at time TL6 (i.e. pulses 31 and 33, respectively,
of timing signal TL6), detector gate 437 applies a one to one input of
gate 432 and carry preset ff 430 is preset to increment the 1.0 minute and
1.0 hour digits, respectively. The logical flow of data from the output of
gate 437 to ff 430 is substantially the same as that already described for
incrementing the data word representing the 0.1 seconds digit and will not
be repeated here.
The preferred embodiment of this invention may be set to operate in either
a 12 hour or 24 hour mode. For operation in a 24 hour mode, the 1.0 and 10
hour digits must be incremented and reset differently than for operation
in a 12 hour mode. Referring again to FIGS. 3a and 4, detector gate 438
applies a one to gate 432 when, at the time TE6 (i.e., the positive pulse
of timing signal TE6), the binary data word representing the 1.0 hour
digit at the output of binary adder 41 reaches a value of four at the same
time the value of the next data word representing the 10 hour digit is two
(i.e., the Q output of A27). At this time, a one is applied to all three
inputs of detector gate 438, and the logical flow of data from the output
thereof to ff 430 is the same as described above for incrementing the data
word representing the 0.1 seconds digit. Carry ff 430 is now preset to
increment the data word representing the 10 hours digit to a value of
three. When the 10 hours digit is incremented to a value of three at time
TE7 (i.e. the positive pulse of timing signal TE7), the output of detector
gate 439 is a zero since a one is applied to all three inputs thereof. The
output of gate 431 becomes a one after inversion by inverting amplifier
440, and the logical flow of data therefrom to ff 430 is the same as
described above. The binary data words representing the 1.0 and 10 hours
digits are reset to zero by auxiliary register 45 which is described
below.
For operation in the 12 hour mode, detector gate 441 monitors the output of
binary adder 41 for a data word having a value of three followed by a data
word having a value of one (i.e. the output of A28) at time TE6. The zero
output of gate 441 is applied to gate 442 which provides a one to gate
432, whereas the output of gate 442 is a zero for 24 hour mode operation.
Auxiliary register 45 resets the value of the data word representing the
1.0 hour digit to a value of one and the value of the data word
representing the 10 hour digit to zero as described below.
The output of binary adder 41 is transmitted to A1 via auxiliary register
45 at every occurrence of a positive pulse of timing signal TM4 whether or
not carry ff 430 is preset to add one to the next digit. Auxiliary
register 45 receives the time data in parallel, wherein the output of
gates 427, 422 and 417 is applied to delay elements AX1, AX2 and AX3 via
gates 457, 458 and 459, respectively. The output of gate 412 is
transmitted to A1 as mentioned above. Since the output of gates 457, 458
and 459 is a one if and only if both inputs are one, inverting amplifier
443 controls the time data value received by the delay elements of
auxiliary register 45 and Al at TM4.
A positive pulse in timing signal TM4 occurs every fourth SLOCK pulse,
SLOCK being the basic timing signal applied to CSR delay elements.
Therefore, for three SLOCK pulses after time data is received by auxiliary
register 45, no new data is received thereby. However, in response to the
three SLOCK pulses occurring between each occurrence of a TM4 pulse,
auxiliary register 45 transmits data serially, AX1 to AX2, AX2 to AX3 to
A1 via gates 460, 461 and 462, respectively. Thus, on the first pulse
after a TM4 pulse, AX1 is empty, AX2 contains the data bit from AX1, AX3
contains the data bit from AX2, A1 contains the data bit from AX3 and A2
contains the data bit from A1. On the third pulse after a TM4 pulse, the
time data has progressed so that AX1, AX2 and AX3 no longer contain time
data and A1 contains the data bit first transmitted to AX1 from gate 427.
On the next occurrence of a TM4 pulse, A1 simultaneously sends that data
bit to A2 and receives a new data bit from gate 412 (i.e. A1 always
contains time data), and AX1, AX2 and AX3 receive new data from gates 427,
422 and 417, respectively.
As mentioned above, inverting amplifier 443 determines the time data values
received by AX1, AX2, AX3 and A1. Unless the output of gate 432 is a one,
the output of inverter 443 is always a zero at a TM4 pulse. Thus, a zero
will be received by AX1, AX2 and AX3 and by A1 unless the output of gate
432 is a one. As described above, the output of gate 442 is a one only
when, in the 12 hour mode, the date word at the output of binary adder 41
has a value of three and the output of A28 has value of one at time TE6.
If the output of gate 442 is a one at a TM4 pulse, a one is transmitted to
A1 by the logical combination of data bits received by gates 463, 454, 455
and inverter 456.
For purposes of the preferred embodiment of this invention display of a six
and a zero in the 10 and 1.0 seconds digits, respectively, would be
improper in any mode. Similarly, in the 12 hour mode, display of a three
or a two in the 1.0 or 10 hour digits or, in the 24 hour mode, display of
a four or a three in the 1.0 or 10 hour digits respectively, would be
improper. Using information received from added controller 43, auxiliary
register 45 corrects the data it receives from binary adder 41 to prevent
display of such data. It should be noted that auxiliary register 45 can
perform its correction function at any arbitrary time data threshold. For
example, if the time-keeping circuit of the present invention were to be
used to record time in units of days, weeks, months and years, it would be
improper for the 1.0 days digits to display an eight. Thus, for this case,
auxiliary register 45 could be set to correct the time data representing
the 1.0 day digit having a value of eight to a value of one.
To understand the correcting function of auxiliary register 45, assume that
the data word at the output of binary adder 41 represents the 10 seconds
digit and has a value of six. In binary format, 0, 1, 1 and 0 appear at
the output of gates 427, 422, and 417 and 412, respectively. As the data
is applied to gates 457, 458, 459, and 453, it is also detected by gate
437. Gate 464 also detects the one at the output of gate 417. The output
of gate 464 is a one unless all inputs are one which only occurs in the 12
hour mode at TE7. Therefore, the output of gate 464 is a one, and, since
the other input of gate 465 is a zero, the output thereof is a one.
Gate 437 applies a one to the input of gate 432 at a positive pulse of
timing signal TL6 timed to coincide with processing of the data
corresponding to this digit. Thus, by the above described analysis for the
10 seconds and 10 minutes digits, carry ff 430 is preset and the output of
gate 433 is a one. Since the output of inverter 443 is a zero, AX1
receives a zero via gate 457, AX2 receives a zero via gate 458 and AX3
receives a zero via gate 459. A1 receives a zero by the logical
combination of data bits received by gates 463, 454, 455, and inverter
456. Therefore auxiliary register 45 has corrected the data representing
the value of the 10 seconds digit from a value of six to a value of zero.
Logic equations which mathematically define operation of the real-time
register described above are presented in Table III.
Table III
______________________________________
Real Time Register Logic Equations
______________________________________
Gate Name Logic Equation
______________________________________
AA1 = -(ACR.A32+-ACR.-A32)
AA2 = -(AAA.A31+-AAA.-A31)
AA3 = -(AAB.A30+-AAB.-A30)
AA4 = -(AAC.A29+-AAC.-A29)
AAA = -(-A32+-ACR)
AAB = -(-A31+-AAA)
AAC = -(-A30+-AAB)
DACR = -(-(PL1.TE6).-(TE7+SA))
SA = -(TM4.TA)
TA = P1+P2+P3+TL6.AA2.AA3+AA2.AA4+PPG
P1 = -(H24+-(TE6.A28.AA1.AA2))
P2 = TE7.AA1.AA2
P3 = TE6.A27.AA3
PPG = AA2.TE7.-H24
PG = -(AA4+-PPG)
JDATE = -(PL1+-(P2+(AA4.PPG)))
ABI1 = PG.SA+AA4.-SA
ABI2 = AB1.SA+AA3.-SA
ABI = AB2.SA+AA2.-SA
ABI4 = AB3.SA+AA1.-SA
IA1 = P1.TM4.F1T1+ABI4.F1T1+E32.F5T1
Flip-Flop Input
Name Type Clock Equation
______________________________________
ACR D TM4 DACR
AB1 D A CLOCK ABI1
AB2 D A CLOCK ABI2
AB3 D A CLOCK ABI3
Al D A CLOCK IA1
A[2:32] D A CLOCK [An].rarw.[An-1]
DATE J/K TM4 J = JDATE
K = TE7
______________________________________
Referring to FIG. 5, stopwatch register 50 is less complex than real-time
register 40, comprising delay elements B1 through B32, binary adder 51,
adder controller 53, and auxiliary register 55. Operation of this register
is substantially the same as that described for real-time register 40
except that unless the HMS signal is applied to gate 531 to enable adder
controller 53 to initiate auxiliary register 55 to correct the data, time
data accumulated will be in units of seconds. With HMS signal applied
(this signal is available from controller 20), stopwatch register 50
accumulates time in units of hours, minutes, seconds and
hundredths-of-seconds (HMS mode) described earlier in this specification.
The output of gate 531 is a one in the HMS mode when the output of binary
adder 51 is at a binary value of six at a positive pulse of timing signal
TL6. The logic equations given in Table IV mathematically define operation
of the stopwatch register.
Table IV
______________________________________
Stopwatch Register Logic Equations
______________________________________
Gate Name Logic Equation
______________________________________
BB1 = -(-BCR.B32+BCR.-B32)
BB2 = -(BAA.B31+-BAA.-B31)
BB3 = -(BAB.B30+-BAB.-B30)
BB4 = -(BAC.B29+-BAC.-B29)
BAA = -(-B32+BCR)
BAB = -(-B31+-BAA)
BAC = -(-B30+-BAB)
BBI1 = -(BB4.-SB)
BBI2 = BB3.-SB+-BB1.SB
BBI3 = BB2.-SB+BBB2.SB
BBI4 = BB1.-SB+BBB3.SB
DBCR = -(TE7+SB)
SB = -(TM4.TB)
TB = -(BB2.BB4+BB2.BB3.TL6.HMS)
IB1 = BBI4.F2T2+E32.F5T2
Flip-Flop Input
Name Type Clock Equation
______________________________________
BCR D TM4 DBCR
BBB1 D BCLOCK BBI1
BBB2 D BCLOCK BBI2
BBB3 D BCLOCK BBI3
B1 D BCLOCK IB1
B[2:32] D BCLOCK [Bn].rarw.[Bn-1]
______________________________________
Referring now to FIG. 6, alarm register 60 comprises delay elements C1
through C32, serial comparator 61, output ff 62, buzzer ff 63 and gates 64
through 69, inverters 72 and 74, and gates 76 through 79. Operation of
this register is mathematically defined by the equations given in Table V.
Table V
__________________________________________________________________________
Alarm Register Logic Equations
__________________________________________________________________________
IC1 = F3T3.C32+F5T3.E32+FIT3.1N
ALS = F1TC.IA1+F2TC.IB1+F4TC.TCOM.ID1+F4TC.TCOM.IA1
JALARM
= IC1.ALS+IC1.ALS
KALARM
= "0"
RALARM
= TM4.TE0.SYNCB
CLBUZ
= TM4.TE0+XK4+XK5
SHIFT IN
= CCLOCK.(FIT5+FIT3)
RBUZ = MODE+RBZR
FLIP-FLOP
ALARM CLOCKED BY CCLOCK
BUZ CLOCKED BY CLBUZ
OUT F CLOCKED BY CLBUZ
C1 to C32
CLOCKED BY CLOCK
__________________________________________________________________________
In the preferred embodiment preselected time data, representing the time at
which an alarm is given, is entered via a calculator keyboard 10 as shown
in FIG. 1. As the preselected time data IC1 circulates in the CSR delay
elements, it is not incremented as in real-time register 40, but rather it
is serially compared with data designated IA1, IB1, and for ID1 from the
other registers via gates 611 and 612. When the data through either of
these gates matches for all 32 bits, the output of gate 613 becomes a zero
and ff 610 applies a zero to the K input of ff 62 and a one to the J input
of ff's 62 and 63. When these ff's are next clocked, the Q output of both
is a one. The Q output of ff 63 may be used then to actuate an audible,
visible or other sensory alarm device. Since comparator 61 can process
data from the real-time and data registers simultaneously, alarm register
60 can be set to give an alarm at a specified time on a particular date in
the future.
Flip-flop 63 is also a source of low frequency periodic signals or
asymetric timing signals. As time data increments in the stopwatch CSR, it
is compared with the preselected data entered into the alarm register CSR
by comparator 61. When the data matches, the signal produced at the Q
output of ff 63 is effective for zeroing the stopwatch CSR when applied to
the BZR input thereof. After zeroing, stopwatch register 50 continues to
increment time data as before. Thus, the Q output of ff 63 becomes a
source of an accurate, stable, low-frequency periodic signal having a
period approximately equal to the real-time required for time data
incrementing in the stopwatch register to equal the time data stored in
the alarm register. Such a signal may be used for testing, calibration or
control purposes.
An asymetric control or timing signal is generated at the Q output of ff 63
in a similar manner. Thirty-two bits of time data from an external
register may be entered into the alarm register CSR via the IN input. When
the time data incrementing in stopwatch register 50 equals the data in
alarm register 60, the stopwatch register CSR is zeroed as described above
and new data is entered into the alarm register CSR from another or the
same external register. The width and repetition rate of the pulses
comprising the signal at the Q output of ff 63 are separately controlled
by appropriately varying the values of data successively entered into
alarm register 60 from one or more external registers. As asymetric timing
signal, corresponding to the values of that data, is then produced by ff
63.
FIG. 7 shows date register 70, which is similar in complexity and operation
to real-time register 40, comprising delay elements D1 through D32, binary
adder 71, adder controller 73 and auxiliary register 75. Adder controller
73 receives date time data from the J Date and Date outputs of real-time
register 40. That data is developed from the logical combination of data
bits received by gates 46, 47, and 48, and ff 49. Refer to Table VI for
the logic equations which mathematically define operation of date register
70.
Table VI
__________________________________________________________________________
Date Register Logic Equations
__________________________________________________________________________
Gate Name
Logic Equation
__________________________________________________________________________
DD1 = -(-DCR.D32+DCR.-D32)
DD2 = -(DAA.D31+-DAA.-D31)
DD3 = -(DAB.D30+-DAB.-D30)
DD4 = -(DAC.D29+-DAC.-D29)
DAA = -(DCR+-D32)
DAB = -(-DAA+-D31)
DAC = -(-DAB+-D30)
DDCR = -(DATE.TE6+JDATE.TE7+DD2.DD4+D28.DK+TE1.DD3+TE3.DD2)
TDD = -(TE1.DD3+TE3.DD2+DD2.DD4+DP1)
DP1 = D28.DK+TE7.DD4
SD = -(TDD.TM4)
DK = -(PX1.PX2+PX1.PX3)
PX1 = -(DD1.DD2.TEZ)
PX2 = -(D27.TEO)
PX3 = -(DD2+(DD1.M31)
CLM = TM4.TE2
IM31 = -(D28.-DD1+-DD1.DD4+-D28.DD1.-DD4)
DBI1 = -(DDR.-SD)
DBI2 = SD.-DB1+-SD.DD3
DBI3 = SD.DB2+-SD.DD2
DBI4 = SD.DB3+-SD.DD1
ID1 = DP1.TM4.F4T4+DBI4.F4T4+E32.F5T4
Flip-Flop Input
Name Type Clock Equation
__________________________________________________________________________
DCR D TM4 DDCR
M31 D CLM IM31
DB1 D DCLOCK DBI1
DB2 D DCLOCK DBI2
DB3 D DCLOCK DBI3
D1 D DCLOCK ID1
D[2:32] D DCLOCK [Dn].rarw.[Dn-1]
__________________________________________________________________________
Referring to FIG. 8, display register 80 comprises delay elements E1
through E32, input 89 and gates 82 through 85 and inverter 86. This
register, operation of which is mathematically defined by the equations
given in Table VII below, receives timing and command signals, and time
data from the other registers via input 89 and provides the data, to
display 81 via output 87. Furthermore, this register, after receiving the
data through input 88 from keyboard 10, inputs original time-setting data
and alarm-setting data to the appropriate registers via output E32.
Table VII
__________________________________________________________________________
Display Register Logic Equations
__________________________________________________________________________
IE1 = F5T5.E32+FET5.BCD+F3T5.C32+F2T5.B32+F4T5.D32+FIT5.IN+
FIT5.A32
BCD = BCD+F5TE.E32
OUT = F3T0.C32+F5T0.E32
Flip-flop
__________________________________________________________________________
E1 to E32 CLOCKED BY ECLOCK
Display 81 may be the same or similar to the LED display with auxiliary
drivers described in U.S. Pat. No. 3,863,060 entitled "General Purpose
Calculator with Capability for Performing Interdisciplinary Business
Calculations," issued on Jan. 28, 1975 to France Rode et al. and assigned
to the assignee hereof.
DETAILED LISTING OF ROUTINES AND SUBROUTINES OF INSTRUCTIONS
A listing of the routines and subroutines of instructions employed by the
real-time, stopwatch and date registers of the time-keeping circuit of the
present invention is given below. The listing also includes a simulation
of time and date accumulations performed by the real-time and date
registers. The real-time data is compressed to decades of seconds for a
period of approximately one-hour 26 minutes as indicated in the third
column of the data. The stopwatch time data shown in the third column is
in units of hours, minutes, seconds and hundredths-of-seconds reading from
left to right. The date time data is formatted as follows:
______________________________________
D = 1 9 7 3 0 1 2 9
Day of the month
Month of the year
Year of the century
No data; no to be displayed
Day of the week*
______________________________________
*The "first" day of the week is assignable by user.
__________________________________________________________________________
DIGITAL SIMULATION SYSTEM
1
2 "TIMING AND A REGISTER SIMULATION"
3 REGISTER
4 DATE,ACR,AB[1:0],AC1:32],
5 PL1,A24,READ,
6 TJMM[6:1],SYNCA,QA1,
7 XKA,XKB,XK[6:1],XI[6:1],CT[3:1].
8 TERMINAL
9 JDATE,KDATE,AA[1:4],ABI[1:4],SR1,AI,AAA,AAB,AAC,SA,TA,PPG,P1,P2,P3
10 SYNC ,SYNCB,DACR,XKK,
11 ADCL,ECLOCK,ACLOCK,BCLOCK,CCLOCK,DCLOCK,
12 PHASEONE,PHASETWO, CLX,JXK4,KXK4,
13 TD[1:9],TE0,TE2,TL6,TE7,TE6,TM4,TM1,TETTM4,TITE7,
14 JXK5,KXK5,JXK6,KXK6,3LOCK.
15 OPERATION
16 LOAD=[
17 A[13].fwdarw.1B1,A[18].fwdarw.1B1,A[16].fwdarw.1B1,A[20].fwdarw.1B1,A
[10].fwdarw.1B1,A[13].fwdarw.1B1,
18 A[21].fwdarw.1B1,A[24].fwdarw.1B1,A[25].fwdarw.1B1,A[28].fwdarw.1B1,A
[29].fwdarw.1B1,A[32].fwdarw.1B1
19 GO=[
20 PHASEONE=-(CT1*-CT2*CT3),
21 PHASETWO=-(CT1*CT2*CT3),
22 CT.fwdarw.(CT(+)1) TAIL 3,
23 TE0=-XT5*-XT4*-XT3,
24 TE2=-XT5*XT4*-XT3,
25 TL6=XT3*XT4+XT3*XT5,
26 TE7=XT5*XT4*XT3,
27 TE6=XT5*XT4*-XT3,
28 TM4=XT2*XT1,
29 TM1=-XT2*-XT1,
30 TETTM4=XT5*XT4*XT3*XT2*XT1,
31 TITE7=-(XT5*XT4*XT3*-XT2*XT1),
32 TD1=TE0,
33 TD2=TE2,
34 TD3=TL6,
35 TD4=TE7,
36 TD5=TE6,
37 TD6=TM4,
38 TD7=TM1,
39 TD8=TETTM4,
40 TD9=TITE7,
41 AAA=-( -A32+-ACR),
42 AAB=-(-A31+-AAA),
43 AAC=-(-A30+-AAB),
44 AA1=-(A32*HCR+-A32*-ACR),
45 AA2=-(A31*AAA+-A31*-AAA),
46 AA3=-(A30*AAB+-A30*-AAB),
47 AA4=-(A29*AAC+-A29*-AAC),
48 P1=-(H24+-(TE6*A28*AA1*AA2)),
49 P2=TE7*AA1*AA2,
50 P3=TE6*A27*AA3,
51 PPG=(AA2*TE7*-H24*TM4),
52 TA=-(P2+P3+TL6*AA2*AA3+AA2*AA4+PPG+P1),
53 SA=-(TM4*TA).
54 KDATE=TE7*TM4,
55 JDATE=-(PL1+-(P2+(AA4*PPG)))*TM4,
56 DATE.fwdarw..uparw.JDATE CON KDATE.uparw.1D0;1D1;-DATE;DATE.,
57 ABI1=4A4*-SA+-(AA4+-PPG)*SA,
58 AB12=AA3*-SA+AB1*SA,
59 ABI3=AA2*-SA+AB2*SA,
60 AB14=AA1*-SA+AB3*SA,
61 DACR=-(-(PL1*TE6)*-(TE7+SA)),
62 .uparw.TM4.uparw.ACR.fwdarw.ACR.,
63 HI=TM4*P1+AB14,
64 AI=TM4*(P1+P3)+ABI4,
65 SR1=AI,
66 .uparw.CT1(=)1.uparw.XKA.fwdarw.-XKA.,
67 XKK=CT1*XKA,
68 .uparw.XKK.uparw.XKB.fwdarw.-XKB.,
69 .uparw.XKK*XKB.uparw.XK1.fwdarw.-XK1.,
70 .uparw.XKK*XKB*XK1.uparw.XK2.fwdarw.-XK2.,
71 .uparw.XKK*XKB*XK1*XK2.uparw.XK3.fwdarw.-XK3.,
72 CLX=XKK*XKB*XK1*XK2*XK3,
73 JXK4=-(XK5*XK6)*CLX,
74 KXK4=CLX,
75 XK4.fwdarw..uparw.JXK4 CON KXK4 .uparw.1D0;1D1;-XK4;XK4.,
76 JXK5=XK4*CLX,
77 KXK5=-(-XK4*-XK6)*CLX,
78 XK5.fwdarw..uparw.JXK5 CON KXK5.uparw.1D0;1D1;-XK5;XK5.,
79 JXK6=CLX* XK4*XK5,
80 KXK6=CLX*-XK4*XK5,
81 XK6.fwdarw..uparw.JXK6 CON KXK6.uparw.1DO;1D1;-XK6;XK6.,
82 SLOCK=1B1,
83 .uparw.SLOCK.uparw.AB1.fwdarw.ABI1.,
84 .uparw.SLOCK.uparw.AB2.fwdarw.ABI2.,
85 .uparw.SLOCK.uparw.AB3.fwdarw.ABI3.,
86 SYNC=TIMM>=45*TIMM<55,
87 .uparw.-PHASETWO.uparw.SYNCA.fwdarw.SYNC.,
88 SYNCB= (XK2*XK3*XK4*XK6+XK5*XK6),
89 ADCL=-(-CT1+-(SYNCA*SYNCB+-SYNCA*-SYNCB)),
90 .uparw.ADCL*-PHASETWO.uparw.TIMM.fwdarw..uparw.TIMM(=)55.uparw.6D0;TI
MM(+)1 TAIL 6..,
91 ACLOCK=SLOCK,
92 BLOCK=SLOCK,
93 CCLOCK=SLOCK,
94 DCLOCK=SLOCK,
95 ECLOCK=-(-SLOCK*-(READ*PHASEONE*-(CLX*XK5*XK6+XK3*-XK4*-XK6))),
96 .uparw.SLOCK.uparw.XT1.fwdarw.-XT1.,
97 .uparw.SLOCK*XT1.uparw.XT2.fwdarw.-XT2.,
98 .uparw.SLOCK*XT1*XT2.uparw.XT3.fwdarw.-XT3.,
99 .uparw.SLOCK*XT1*XT2*XT3.uparw.XT4.fwdarw.-XT4.,
100 .uparw.SLOCK*XT1*XT2*XT3*XT4.uparw.XT5.fwdarw.-XT5.,
101 A.fwdarw.AI CON A[1:31],
102 QA1=XT(=)2*A31*-A30*-A29*-A28,
103 .uparw.DATE.uparw.OUTPUT(6,A,XT,DATE).,
104 .uparw.XT(=)3.uparw.OUTPUT(6,A,DATE).
105 ].
106 CONTROl
107 XA1:GO,->XA2/
108 XA2:.uparw.QA1.uparw.->XA3;->XA1./
109 XA3:LOAD,->XA1/.$
END OF TRANSLATION, 0 ERRORS.
*TIME=6 STATE=XA1:
A=00000000
*TIME=7A
STATE=XA1:
A=00000000
*TIME=135
STATE=XA1:
A=00000999
*TIME=199
STATE=XA1:
A=00001000
*TIME=264
STATE=XA1:
A=00001999
*TIME=328
STATE=XA1:
A=00002000
*TIME=399
STATE=XA1:
A=00002999
*TIME=457
STATE=XA1:
A=00003000
*TIME=522
STATE=XA1:
A=00003999
*TIME=586
STATE=XA1:
A=00004000
*TIME=651
STATE=XA1:
A=00004999
*TIME=715
STATE=XA1:
A=00005000
*TIME=780
STATE=XA1:
A=00005999
*TIME=844
STATE=XA1:
A=00010000
*TIME=909
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