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Claims  |
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We claim:
1. A digital vocoder comprising:
a transmitter including
a source of speech,
an analog to digital converter coupled to said source to provide a first
digital representation of said speech,
an adaptive filter coupled to said analog to digital converter to derive
from said first digital representation of said speech a digital prediction
residual signal and digital spectral parameters,
a pitch period extraction circuit coupled to one output of said adaptive
filter responsive to said residual signal to produce a first digital
excitaion signal representing the pitch period of said speech,
a voiced/unvoiced decision circuit coupled to said adaptive filter and said
pitch period extraction circuit to produce a second digital excitation
signal indicating when said speech is voiced and when said speech is
unvoiced,
an arrangement coupled to another output of said adaptive filter to produce
a digital number representing the gain of said adaptive filter, and
a multiplexing and transmitting arrangement coupled to said adaptive
filter, said pitch period extraction circuit and said voiced/unvoiced
decision circuit to time multiplex and transmit said digital spectral
parameters, said first and second digital excitation signals and said
digital number; and
a receiver including
a receiving and demultiplexing arrangement coupled to said multiplexing and
transmitting arrangement to receive and separate from each other said
digital spectral parameters, said first and second digital excitation
signals and said digital number,
an excitation generator coupled to said receiving and demultiplexing
arrangement responsive to said first and second digital excitation signals
and said digital number to produce a third digital excitation signal.
a receive filter coupled to said excitation generator and said receiving
and demultiplexing arrangement responsive to said digital spectral
parameters and said third excitation signal to provide a second digital
representation of said speech which is substantially identical to said
first digital representation of said speech, and
a digital to analog converter coupled to said receive filter to provide a
speech output substantially identical to said speech of said source.
2. A vocoder according to claim 1, wherein
said digital spectral parameters are N digital signals each representing a
different weighting coefficient of said adaptive filter, where N is an
integer greater than 1.
3. A vocoder according to claim 2, wherein
said adaptive filter includes
N stages of an Itakura type cascade.
4. A vocoder according to claim 3, wherein
each of said stages includes
a residual calculator providing a forward residual output and a backward
residual output, and
a correlation calculator coupled to the input of said residual calculator
to operate on said forward and backward residual outputs of the previous
one of said residual calculators; and
a divide circuit having inputs coupled to the outputs of said correlation
calculator and an output coupled to said residual calculator and said
divide circuit provides said weighting coefficient.
5. A vocoder according to claim 4, wherein
each of said residual calculators, each of said correlation calculators and
said divide circuits include
a repetitive serial arithmetic logic units.
6. A vocoder according to claim 5, wherein
said receive filter includes
N/2 logic stages connected in cascade with respect to each other and said
third excitation signal with a first feedback arrangement between adjacent
ones of said stages and a pair of feedback arrangement in each of said
stages, each of said N/2 logic stages being coupled to said receiving and
demultiplexing arrangement to operate on a different adjacent pair of said
N weighting coefficients on a time sharing basis to provide said second
digital representation of said speech.
7. A vocoder according to claim 6, wherein
each of said N/2 logic stages include
repetitive serial arithmetic logic units.
8. A vocoder according to claim 1, wherein
said transmitter further includes
a linear to log code converter coupled between said arrangement and said
multiplexing and transmitting arrangement to convert said digital number
to a log code representing said gain; and
said receiver further includes
a log to linear code converter coupled between said receiving and
demultiplexing arrangement and said excitation generator to convert said
log code to a linear code representing said gain.
9. A vocoder according to claim 1, further including
a pitch period correction circuit coupled to said pitch period extraction
circuit and said voiced/unvoiced decision circuit to eliminate any large
changes in said pitch period and thereby improve the quality of said
speech output of said digital to analog converter.
10. A transmitter for a digital vocoder comprising:
an analog to digital converter coupled to a source of speech to provide a
digital representation of said speech;
an adaptive filter coupled to said converter to derive from said digital
representation of said speech a digital prediction residual and digital
spectral parameters;
a pitch period extraction circuit coupled to one output of said filter
responsive to said residual signal to produce a first digital signal
representing the pitch period of said speech;
a voiced/unvoiced decision circuit coupled to said filter and said
extraction circuit to produce a second digital excitation signal
indicating when said speech is voiced and when said speech is unvoiced;
an arrangement coupled to another output of said filter to produce a
digital number representing the gain of said adaptive filter; and
a multiplexing and transmitting arrangement coupled to said filter, said
extraction circuit and said decision circuit to time multiplex and
transmit said digital spectral parameters, said first and second digital
excitation signals and said digital number.
11. A transmitter according to claim 10, wherein
said digital spectral parameters are N digital signals each representing a
different weighting coefficient of said filter, where N is an integer
greater than 1.
12. A transmitter according to claim 11, wherein
said filter includes
N stages of an Itakura type cascade.
13. A transmitter according to claim 12, wherein
each of said stages include
a residual calculator providing a forward residual output and a backward
residual output, and
a correlation calculator coupled to the input of said residual calculator
to operate on said forward and backward residual outputs of the previous
one of said residual calculators; and
a divide circuit having inputs coupled to the outputs of said correlation
calculator and an output coupled to said residual calculator and said
divide circuit provides said weighting coefficient.
14. A transmitter according to claim 13, wherein
each of said residual calculators, each of said correlation calculators and
each of said divide circuits include
repetitive serial arithmetic logic units.
15. A transmitter according to claim 10, wherein
said transmitter further includes
a linear to log code converter coupled between said arrangement and said
multiplexing and transmitting arrangement to convert said digital number
to a log code representing said gain.
16. A transmitter according to claim 10, further including
a pitch period correction circuit coupled to said pitch period extraction
circuit and said voiced/unvoiced decision circuit to eliminate any large
changes in said pitch period and thereby improve the quality of said
speech output of said digital to analog converter.
17. A receiver for a digital vocoder comprising:
a receiving and demultiplexing arrangement to receive a serial digital
pulse train containing digital spectral parameters derived in an adaptive
filter at a transmitter from input speech, first and second digital
excitation signals derived at said transmitter from said adaptive filter
and a log coded digital number representing gain in said adaptive filter
and to separate the contents of said pulse train;
an excitation generator coupled to said arrangement responsive to said
first and second excitation signals and said digital number to produce a
third excitation signal;
a receive filter coupled to said generator and said arrangement responsive
to said digital spectral parameters and said third excitation signal to
provide a digital representation of speech; and
a digital to analog converter coupled to said filter to provide a speech
output which is substantially identical to said input speech.
18. A receiver according to claim 17, wherein
said digital spectral parameters are N digital signals each representing a
different weighting coefficient of said adaptive filter, where N is an
integer greater than 1.
19. A receiver according to claim 18, wherein
said receive filter includes
N/2 logic stages connected in cascade with respect to each other and said
third excitation signal with a first feedback arrangement between adjacent
ones of said stages and a pair of feedback arrangement in each of said
stages, each of said N/2 logic stages being coupled to said receiving and
demultiplexing arrangement to operate on a different adjacent pair of said
N weighting coefficients on a time sharing basis to provide said digital
representation of speech.
20. A receiver according to claim 19, wherein
each of said N/2 logic stages include
repetitive serial arithmetic logic units.
21. A receiver according to claim 20, wherein
said receiver filter further includes
a log to linear code converter coupled between said arrangement and said
generator to convert said digital number to a linear code representing
said gain.
22. A receiver according to claim 17, wherein
said receiver filter further includes
a log to linear code converter coupled between said arrangement and said
generator to convert said digital number to a linear code representing
said gain. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates to speech communication systems and more
particularly to a vocoder type speech communication system.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved vocoder.
Another object of the present invention is to provide a digital vocoder
having a hardware implementation using a multi-processing design with
repetitive serial arithmetic units.
A feature of the present invention is the provision of a digital vocoder
comprising: a transmitter including a source of speech, an analog to
digital converter coupled to the source to provide a first digital
representation of the speech, an adaptive filter coupled to the analog to
digital converter to derive from the first digital representation of said
speech a digital prediction residual signal and digital spectral
parameters, a pitch period extraction circuit coupled to the adaptive
filter to produce a first digital excitation signal representing the pitch
period of the speech, a voiced/unvoiced decision circuit coupled to the
adaptive filter and the pitch period extraction circuit to produce a
second digital excitation signal indicating when the speech is voiced and
when the speech is unvoiced, an arrangement coupled to the adaptive filter
to produce a digital number representing the gain of the adaptive filter,
and a multiplexing and transmitting arrangement coupled to the adaptive
filter, the pitch period extraction circuit and the voiced/unvoiced
decision circuit to time multiplex and transmit the digital spectral
parameters, said first and second digital excitation signals and the
digital number; and a receiver including a receiving and demultiplexing
arrangement coupled to the multiplexing and transmitting arrangement to
receive and separate from each other the digital spectral parameters, the
first and second digital excitation signals and the digital number, an
excitation generator coupled to the receiving and demultiplexing
arrangement responsive to the first and second digital excitation signals
and the digital number to produce a third digital excitation signal, a
receive filter coupled to the excitation generator and the receiving and
demultiplexing arrangement responsive to the digital spectral parameters
and the third excitation signal to provide a second digital representation
of the speech which is substantially identical to the first digital
representation of the speech, and a digital to analog converter coupled to
the receive filter to provide a speech output substantially identical to
the speech of the source.
Another feature of the present invention is the provision of a transmitter
for a digital vocoder comprising: an analog to digital converter coupled
to a source of speech to provide a digital representation of the speech;
an adaptive filter coupled to the converter to derive from the digital
representation of the speech to digital prediction residual and digital
spectral parameters; a pitch period extraction circuit coupled to the
filter to produce a first digital signal representing the pitch period of
the speech; a voiced/unvoiced decision circuit coupled to the filter and
the extraction circuit to produce a second digital excitation signal
indicating when the speech is voiced and when the speech is unvoiced; an
arrangement coupled to the filter to produce a digital number representing
the gain of the adaptive filter, and a multiplexing and transmitting
arrangement coupled to the filter, the extraction circuit and the decision
circuit to time multiplex and transmit the digital spectral parameters,
the first and second digital excitation signals and the digital number.
Still another feature of the present invention is the provision of a
receiver for a digital vocoder comprising: a receiving and demultiplexing
arrangement to receive a serial digital pulse train containing digital
spectral parameters derived in an adaptive filter at a transmitter from
input speech, first and second digital excitation signals derived at the
transmitter from the adaptive filter and a log coded digital number
representing gain in the adaptive filter and to separate the contents of
the pulse train; an excitation generator coupled to the arrangement
responsive to the first and second excitation signals and the digital
number to produce a third excitation signal; a receive filter coupled to
the generator and the arrangement responsive to the digital spectral
parameters and the third excitation signal to provide a digital
representation of speech; and a digital to analog converter coupled to the
filter to provide a speech output which is substantially identical to the
input speech.
BRIEF DESCRIPTION OF THE DRAWING
Above-mentioned and other features and objects of this invention will
become more apparent by reference to the following description taken in
conjunction with the accompanying drawing, in which:
FIG. 1 is a general block diagram of a digital vocoder in accordance with
the principles of the present invention;
FIG. 2 is a more specific block diagram of the digital vocoder of FIG. 1;
FIG. 3 is a still more specific block diagram of the transmitter of the
digital vocoder of FIG. 2;
FIG. 4 is a block diagram of the residual calculator of FIG. 3;
FIG. 5 is a block diagram of the correlation calculator of FIG. 3;
FIG. 6 is a block diagram of the divide circuit of FIG. 3;
FIG. 7 illustrates the algorithm block diagram of the voiced/unvoiced
decision circuit of FIG. 3;
FIG. 8 illustrates the voiced/unvoiced decision algorithm flow chart
defining the various decisions to be made by the block diagram of FIG. 7;
FIG 9 is an algorithm block diagram of the pitch period correction circuit
of FIG. 3;
FIG. 10 illustrates the pitch period correction circuit algorithm flow
chart defining the various decisions to be made by the block diagram of
FIG. 9;
FIG. 11 is a still more specific block diagram of the receiver of the
digital vocoder of FIG. 2;
FIG. 12 is a block diagram of a receive filter stage of FIG. 11;
FIG. 13 is a block diagram of the excitation signal generator of FIG. 11;
FIG. 14 is a block diagram of the parameter interpolator of FIG. 11;
FIG. 15 is a block diagram of the linear to log code converter of FIG. 3;
FIG. 16 is a block diagram of the log to linear code converter of FIG. 11;
FIG. 17 is a block diagram of an adder and a subtractor circuit employed as
one of the building blocks of the foregoing figures of the drawing;
FIG. 18 is a block diagram of a multiplier which is another building block
employed in the foregoing figures of the drawing;
FIG. 19 is a block diagram of the low pass filter of FIG. 2;
FIGS. 20A and 20B, when organized as illustrated in FIG. 20C, is the flow
chart of the pitch period extraction algorithm in accordance with the
principles of the present invention;
FIG. 21 illustrates and defines logic symbols employed in FIGS. 22 and 23;
FIG. 22 is a logic diagram of a decision circuit as employed in FIG. 23;
and
FIGS. 23A through 23J, when organized as illustrated in FIG. 23K, is a
logic diagram implementing the algorithm of FIGS. 20A and 20B.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 illustrates the basic block diagram of the digital vocoder in
accordance with the principles of the present invention. Speech input to
the transmitter is sampled and converted to a digital representation in
the analog to digital converter 1. Spectral parameters are derived from
transmit filter 2 and excitation parameters are derived from pitch period
extraction circuit 3 and the voiced/unvoiced decision circuit 4. The
spectral parameters and excitation parameters are multiplexed in
multiplexer 5 and transmitted to the receiver over transmission path 6.
The transmit multiplexed signal is demultiplexed and the receiver is frame
synchronized in demultiplexer and frame sync circuit 7. The excitation
parameters and spectral parameters are coupled to excitation generator 8
and receive filter 9, respectively, to synthesize digital speech. The
digital speech is then coupled to digital to analog converter 10 to
recover the analog speech for utilization. All processing from converter 1
in the transmitter to converter 10 in the receiver is digital and
implemented with logic circuits.
Transmit filter 2 contains an adaptive filter or predictor which forms an
estimate of a present input speech sample from stored values of previous
input speech samples. This estimate is subtracted from the present input
sample giving a prediction error or prediction residual which is one of
the transmit filter outputs. The receive filter 9, an adaptive filter or
predictor, has a transfer function which is inverse to that of the
transmit filter 2.
The prediction of the present speech sample in transmit filter 2 is a
weighted sum of previous input samples. The weighing coefficients are the
spectral parameters of filter 2. A least squares adaption algorithm is
used to continuously adapt these parameters to the changing
characteristics of the input speech sounds.
The adaption algorithm calculates the weighting coefficients from
continuously updated correlation coefficients of successive speech
samples.
The weighting coefficients in transmit filter 2 are called spectral
parameters because they contain the same short term spectral information
obtained by a filter bank in a conventional vocoder. The advantage of
using the adaptive predictor or filter instead of a filter bank or its
equivalent is that the predictor parameters (the spectral parameters)
provide an accurate representation of the various resonances, or formants,
in the speech spectrum with far fewer parameters than required with a
filter bank. Typically, only 8 or 10 spectral parameters are required to
give a complete spectral representation of the speech over a standard
4,000 hertz channel bandwidth.
The pitch period extraction circuit 3 responds to the prediction residual
at the output of filter 2, rather than the speech input to provide the
pitch period as one of the excitation parameters.
Referring to FIG. 2, there is illustrated a more detailed block diagram of
the digital vocoder in accordance with the principles of the present
invention. A selected multiprocessing system design has been incorporated
in implementing the block diagram of FIG. 2 and each of the blocks or
sub-systems shown therein exist as physical entities since there is no
common time-shared equipment.
The transmitter input circuit includes a handset mike 11 coupled to a vogad
amplifier 12 whose output is coupled to a low pass filter 13. The output
of filter 13 is coupled to a sample and hold circuit 14. The output of
circuit 14 is coupled to a 12 bit analog-to-digital converter 15, which
converts the speech to the digital format required for further operation
thereon. The output circuit of the transmitter contained in block 16
labeled "MULTIPLEXER" includes holding registers for the speech
parameters, and multiplexing and synchronizing circuits to serially
transmit the speech data.
Four major functions are implemented within the digital vocoder
transmitter. These are the adaptive filter 17 (transmit filter 2 of FIG.
1), pitch extraction including squarer and low pass filter 18 and pitch
period extraction circuit 19. To the output of circuit 19 is coupled pitch
period correction circuit 20 and a voiced/unvoiced decision circuit 21. It
should be noted that squarer and low pass filter 18 are coupled to the
residual output of the 10th stage of filter 17 and that the inputs to
circuit 21 are pitch peak amplitude from circuit 19, the output S.sub.o of
converter 15 and the residual power output from the 10th stage of filter
17.
The digital speech from converter 15 is applied to the input of the
adaptive filter. Filter 17 includes ten identical cascaded stages, each of
which calculate their filter stage weight, as described hereinbelow with
respect to FIGS. 3, 4, 5 and 6. Adaptive filter 17 is a 10 stage Itakura
type cascade derived from Equation (1) of an article by F. Itakura and S.
Saito, "Digital Filtering Techniques for Speech Analysis and Synthesis",
pages 261-264, Paper C25C1, Seventh International Congress or Acoustics,
Budapest, 1971.
The prediction residual from the last stage of filter 17 is squared and
filtered in squarer and low pass filter 18 before being applied to the
input of circuit 19. The derived pitch period data is then applied to the
pitch correction circuit 20. The amplitude of the pitch peaks of the
squared and low pass filtered residual, together with the rms (root means
square) value of the input speech and residual power form the input to the
voiced/unvoiced decision circuit 21. The voicing decision is applied to
pitch correction circuit 20 for possible correction therein before being
transmitted.
The residual power output from the 10th stage of filter 17 is applied to
linear to log code converter 22 to provide a digital number representative
of the gain of the filter which is also coupled to multiplexer 16 to be
transmitted to the receiver in the multiplexed format.
The input circuit to the receiver includes demultiplexer and frame sync
circuit 23. The receiver output circuit includes a 12 bit
digital-to-analog converter 24, a low pass filter 25, a buffer amplifier
26 and the headset earphone 27. A linear interpolator 28 performs an
interpolation on the received speech parameter data to obtain excitation
and filter parameter updates at a rate four times the transmit update or
frame rate. The operations performed in the receive filter 29 (receive
filter 9 of FIG. 1) are basically the inverse of that performed in the
adaptive filter of transmit filter 17. Excitation generator 30 supplies
one input signal to receive filter 29. The excitation is either a series
of pulses determined by the pitch period parameter for a voiced condition
or by random noise pulses for an unvoiced condition. The weighted
coefficients W1-W10 are other inputs to filter 29.
Referring to FIG. 3, there is illustrated therein a still more specific
block diagram of the transmitter of the digital vocoder of the present
application. Timing and control signals for all circuits of the
transmitter are derived from a pre-programmed read-only memory module
accessed at an 800 khz (kilohertz) rate. The program is controlled by
program counter 31 which controls the read-only memory 32. The output data
word from memory 32 is stored in holding register 33 clocked by the 800
khz signal thereby ensuring synchronization of all control and timing
signals.
TABLE I
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PARAMETER CODING AND MULTIPLEXING
Total and Spectral Parameters Only, Number of Bits Per Frame
UPDATE TRANSMISSION RATE
INTERVAL 4800 B/S 3600 B/S 2400 B/S
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10 MS 48 36
15 72(57) 54
20 96(81) 72(57) 48(33)
25 90 60(45)
30 72(57)
EXCITATION PARAMETERS
Pitch Period 7
Residual Level
6
Voicing Parameter
1
Framing 1
TOTAL 15
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Table I lists the code formats for three data rates; namely, 4800, 3600 and
2400 bits per second.
TABLE II
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QUANTIZING RULES
RULE
NO. OF
BITS PER COEFFICIENT
NO. STAGES
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10
W11 W12
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(For Total Number of Bits = 33)
A1 8 7 6 4 3 3 3 3 3 0 0 0 0
A2 10 6 5 3 3 3 3 3 3 2 2 0 0
A3 10 5 4 3 3 3 3 3 3 3 3 0 0
A4 8 8 7 3 3 3 3 3 3 0 0 0 0
A5 8 5 4 4 4 4 4 4 4 0 0 0 0
A6 8 6 5 4 4 4 4 3 3 0 0 0 0
(For Total Number of Bits = 57)
B1 12 5 5 5 5 5 5 5 5 5 5 4 3
B2 10 6 6 6 6 6 6 6 5 5 5 0 0
B3 10 8 7 6 6 5 5 5 5 5 5 0 0
B4 8 8 8 8 7 7 7 6 6
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Table II shows the rules for different parameter coding conditions. Best
results are obtained by making the number of bits for the lower order
parameters, W1, W2 etc., as high as possible even at the expense of the
higher order of parameters W7, W8, etc. In particular, rules A6 and B3
were found to be the best for 33 and 57 bit coding. It was further found
that using fewer bits for quantizing caused greater degradation in speech
quality than using a longer update interval. Therefore the 72-bit frame
was selected, which corresponds to 15, 20, and 30 millisecond update
intervals for the data rates of 4800, 3600, and 2400 bits per second,
respectively. The reflection coefficients whose magnitude does not exceed
one are coded with 57 bits, using rule B3 where there are 8, 7, 6, 6, 5,
5, 5, 5, 5, 5 bits for the first through tenth coefficient. The excitation
parameters are coded with 7 bits for pitch period, 6 bits for mean square
prediction residual with approximately logarithmic coding, and 1 bit each
for voicing and frame sync information.
A full operation cycle of the transmitter corresponding to a 125
microsecond sample period, consists of 90 individual operations or
instructions of 1.38 microsecond duration each. The adaptive filter 17,
squarer and low pass filter 18 and pitch period extraction circuit 19
repeat these operations each sample period, while the voice decision
carried out in circuit 21 and the pitch period correction circuit 20 are
activated once every 40 samples and require a full sample period to
complete their functions.
Functionally, the output of converter 15 (FIG. 2) consists of a 12 bit word
in 2's complement format and forms the input to the first stage of the
cascade transmit filter or adaptive filter 17. Within filter 17 residuals
and correction coefficients are calculated in calculators 34 and 35,
respectively, for each stage of filter 17 with the calculation taking
place every sample period and each filter weight is calculated by a divide
circuit 36 from the output of correlation calculator 35 and updated in the
corresponding residual calculator 34 each sample period. Each filter
weight therefore gets updated every sample period. The residual from the
tenth stage, namely, from calculator 34', which is a 16 bit serial 2's
complement word, forms the input to squarer and low pass filter 18. Both
the input signal power and residual power are calculated from the outputs
of the first and last correlation calculator stages, and stored in adding
and holding registers 37 and 38, respectively. These parameters are
updated once every 40 samples during the same cycle weight W1 is
calculated and stored in holding register 39. In addition, the eight most
significant bits of the calculated weight W1 through W10 are stored in
holding registers 40. The output of excitation signal analyzer 41 includes
a one bit voiced/unvoiced decision and an eight bit unsigned pitch period
which updates the multiplexer holding register 42 once every 40 samples.
In addition, the logarithm to the base two of the square root of the
residual power is calculated in linear to log code converter 22 and stored
in holding register 43. The output of converter 22 is a 6 bit unsigned
integer. A sync sequence generator 44 provides the synchronization
information for the receiver and is coupled to the multiplexer which is in
the form of a 72 bit parallel in/serial out register 45. The digital words
from registers 40, 42 and 43 are coupled to a quantizing rule patch 46
which adjusts the number of bits for the weighting coefficients W1 and W10
according to the quantizing rules in Table II. According to the present
example, rule B3 is employed which provides the number of bits for each of
the coefficients as illustrated in Table II.
Referring to FIG. 4, there is disclosed therein the block diagram of one of
the residual calculators 34 implementing filter 17. Filter 17 includes ten
residual calculators and ten correlation calculators and ten dividers
(divider circuit 36). The residual calculator and correlation calculator
of each stage operate individually on the same input data. The output of
the correlation calculator forms the input to divider circuit, which
calculates the filter weighting coefficient. The updated value of the
weighting coefficients is loaded into holding register 47 at the beginning
of every sample cycle. The remainder of the cycle consists of the serial
multiplication of the weight with the forward residual in multiplexer 48
and the backward residual in multiplexer 49 after passing through a
sixteen bit shift register 50 and subtracting the resulting products from
the backward and forward residual in subtractors 51 and 52, respectively.
The residuals are 16 bit numbers represented in 2's complement format and
the weighting coefficients are 12 bit numbers in signed magnitude format.
Multipliers 48 and 49 are therefore 12 .times. 16 multipliers. The
resulting answer is truncated to 16 bits and delayed by one sample period
before application to the following stage through shift registers 53 and
54.
Referring to FIG. 5, there is illustrated therein a functional block
diagram of a correlation calculator. This circuit is repeated twice in
each stage with the adder 55 at the input of the circuit being replaced by
a subtractor in one of the two circuits, resulting in the calculation of
both the average value of the sum and difference of the forward and
backward residuals.
Three separate operations are performed in the correlation calculator
circuit. First, one half of the sum or difference of the residual is
calculated serially and stored in a 16 bit shift register 56. The factor
of one half is required to ensure no register overflows will occur. The
absolute value of the result sum or difference is then formed serially in
format converter 56' and loaded into the multiplicand shift register 56
and multiplier holding register 57. At this point the updated calculation
of the correlation coefficients begins. The square of the sum or
difference is calculated serially and subtracted from the previous value
of the correlation coefficients in subtractor 58. The previous values of
the correlation coefficients are stored in shift register 59. The
resultant differences are then divided by 64 and added to the previous
values of the correlation coefficients by adder 60. Division by 64 is
accomplished by delaying the previous correlation coefficient by 6 bits
relative to the differences. The newly calculated coefficients are stored
in a 32-bit shift register 59. The circuit requires a 16 .times. 16
multiplier module 61 and results in a 32 bit correlation coefficient.
Referring to FIG. 6, there is illustrated therein the block diagram of a
divide circuit. The filter weighting coefficient is calculated as one half
the difference divided by one half the sum of the calculated correlation
coefficients. The weighting coefficient is calculated as a 12 bit signed
magnitude integer having a range of .+-.1. Illegal divide operations; that
is, divisions whose resulting quotient would exceed the weighting range,
are detected and a value of zero is returned for the weight coefficient.
The divide circuit operates as follows. At the beginning of each sample
period, the serial outputs of the correlation calculator stage are applied
to the divider circuit. The absolute value of the sum and difference of
the correlation coefficients as provided by subtractor 66 and adder 67 are
found and loaded into the divisor and dividend holding registers 63 and
64. In addition, the sign of the resulting quotient is determined. The
division is accomplished by a series of successive subtractions and
shifts. Functionally, the divisor is first subtracted from the dividend. A
positive difference is detected as an illegal divide and the quotient is
set to zero. A negative difference results in the multiplication of the
dividend by 2. The operation is then repeated to determine the most
significant bit of the quotient. A positive difference causes the quotient
bit to be set to "1" and the difference to be loaded into the dividend
register 63. A negative difference causes the quotient bit to be set to
"0" and the dividend to be multiplied by 2. The operation is then repeated
for the lower order bits of the quotient in adder 65. The division
requires one sample period.
The squarer and low pass filter 18 and pitch period extraction circuit 19
are fully described hereinbelow with respect to FIGS. 19, 20 and 23.
Referring to FIG. 7, there is disclosed therein a block diagram for the
algorithm for the voiced/unvoiced decision circuit which includes
comparison and decision circuits 68 and algorithm combinatorial logic 69.
The inputs to comparison and decision circuits 68 includes four lines of
serial data, one of which, namely, W1 has 12 bits, the other three inputs
having 32 bits each. Referring to the block diagram, these three inputs
are RES, PWR, and NUMRAT. The one bit serial output, the V/UV decision
(IPRV) is then available 36 clock pulses after the data appears at the
inputs. The V/UV function is accessed (subject to an update) every 40
samples.
The voiced/unvoiced algorithm is shown in FIG. 8 and requires eight
decisions which are made by employing a serial comparator. The comparator
subtracts one input from the other and clocks the sign of the difference
into a flip-flop to be used as the decision. Inputs to the algorithm are
generated in other portions of the vocoder as indicated by the labels of
the input of FIG. 7. These inputs are used in the comparisons along with
certain constants representing threshold levels. Once all decisions have
been determined, they are fed to a logical equivalent of the flow chart
which is the logic square of FIG. 7 which then produces the answer: either
a 1 or 0 for voiced or unvoiced, respectively, at the output.
Referring to FIGS. 9 and 10, there is illustrated therein the inputs and
outputs to the pitch period correction circuit 70 and the flow chart of
the pitch period correction algorithm. Pitch period correction circuit 70
functions basically in the same manner as the pitch period extraction
circuit fully disclosed in FIGS. 20 and 23 and the description thereof.
There, however, is one difference which changes, slightly, the character
but not the basic operation of the hardware.
The difference is stated as follows. There exists, in the pitch period
correction algorithm, a need to multiply two variables and also multiply
this product by a constant. The serial multiplier requires that it be
loaded before serial multiplication can take place. Provision must be made
for additional time in the cycle in which to clock the multiplicand
through the multiplier circuit. The time required to multiply this result
by the constant 0.0045 must also be provided.
There are four serial inputs to the pitch correction function. The inputs
INRP and IPRP are the raw pitch periods from the previous sample and the
sample before that. These signals are both 13 bit words, and are received
from the pitch period extraction circuit. The signal PWR is the power of
the original voice, a 32-bit serial word, and is taken from the first
stage of the transmit filter correlation calculator. The last input, IRPV,
is the one bit raw voicing decision.
The pitch period correction circuit itself, as mentioned above, functions
in a manner similar to the pitch period extraction circuit and, therefore,
is shown as a single functional box. There are only two outputs from this
circuit, namely, PP and V/UV. The signal PP represents the pitch period
from two samples prior to the present sample (the total excitation signal
generator has a two sample delay and is a serial 13-bit word). The other
output, V/UV, is a single bit voicing decision which is the output from
the V/UV decision circuit which has been processed by the correction
circuit. Both outputs are updated every sample and comprise the final
realization of the excitation signal analyzer 41 of FIG. 3. These signals
are sent to the multiplexer circuit for transmission where they are
sampled every 5 miliseconds.
The pitch period correction algorithm of FIG. 10 improves the quality of
the synthesized speech by eliminating any large changes in the pitch
period from one update interval to the next. The algorithm operates by
using raw pitch and voiced/unvoiced data, obtained from the pitch period
extractor and voiced/unvoiced decison circuit and modifying it in
accordance with prescribed criteria.
The final pitch period and voicing decision outputs of the algorithm are
referred to as the calculated data. The inputs are the raw data. The
algorithm uses the present raw data and the previous, one sample back, raw
and calculated data to determine the values of the present calculated
data. The power of the original speech and two calculated parameters, IDIF
and ITH, are also used as criteria to determine the smoothed output. After
a decision is made on the value of calculated pitch, a final decision is
made on voicing depending on the value of the power of the original
speech. If the power is below a predetermined level, the speech is assumed
unvoiced.
Referring to FIG. 11, there is disclosed therein a block diagram in greater
detail of the receiver of the digital vocoder of this invention. As in the
transmitter, timing and control signals are derived from a preprogrammed
read-only memory module synchronized by the timing recovery circuit 71.
The receive read-only memory in circuit 71 is accessed at a 576 khz rate
and a full operation cycle, corresponding to the 125 microsecond sample
period, consists of 72 individual operations of 1.73 microseconds duration
each. The received data is coupled to a demultiplexer which is illustrated
to be a 72-bit serial in/parallel output register 72, whose parameter
outputs are coupled to quantizing role patch 73 which operates in an
inverse relationship to the quantizing rule patch 46 of the transmitter to
return all of the weighting coefficients to the same number of digits in
accordance with the empl | | |
