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BACKGROUND OF THE INVENTION
The invention relates to programmable sequence control operation for
machines, and processes such as industrial machines or processes and it
relates more particularly to high-security programmable sequence control
apparatus, systems and methods.
It is known to control an industrial process sequentially, e.g. to cause
the performance of a series of machine functions or process operations
such that some of the steps will not be performed unless a predetermined
event, which can be an earlier step, has occurred. Sequential control can
be achieved with a stored set of program instructions successively read
out and executed, and such control requires that at times these
instructions provide for jumping, or branching out of the succession.
Sequence controllers are well known, and an overview of the state of the
prior art can be found in "Programmable Logic Controllers -- an Update" by
N. Andreiev in Control Engineering of September, 1972, pages 45-47 and in
"Programmable Logic Controllers-Painless Programming to Replace The Relay
Bank" by G. Lapidus in Control Engineering of April 1971, pages 49-60. If
the memory is programmable, a given hardware apparatus can be instantly
adapted to fit a particular industrial process. Sequence controllers can
be hard-wired, or they may use software coordinating logic elements used
for decision and control. In a digital controller, conversation between
the functional units is accomplished essentially by binary logic according
to Boolean algebra. As a result of such logic steps, a logic decision is
taken involving input conditions and output commands which admit of only
two opposite states such as yes or no, do or do not, true or false, on or
off. These states pertain for instance to limit switches, relay, valves or
other such two-state power devices which are associated with the
controlled process. A sequence controller can establish a predetermined
sequence of outputs, each in one of two states, which is used to control a
machine or a process and in this respect a sequence controller is
distinguishable from other control systems which perfom data handling,
logging or monitoring functions. The latter are generally associated with
more complex control systems involving computation of data such as found
in adaptive process control, for instance.
In contrast, a rather simple structural organization is practical with
sequence controllers, although sequence controllers may be found also
within more complex control systems, particularly in digital computer
systems. As a result of this relative conceptual simplicity, efforts have
been made in the past to reduce the structural combination to that
essential for cost reduction and increased reliability. This trend is
better represented by a combination of read-only-memory (ROM) units and a
software translation, with coded instructions stored therein, of the logic
coordination of the input and output signal units. Still, versatility and
reliability demand a certain degree of comlexity which must be attained at
the lowest cost as well as within the constraints of the simple basic
structure of a sequence controller e.g. a short word length, a limited
capacity for the memory, and, as a result, the availability of only a few
elementary instructions.
Amond the requirements which need to be satisfied for the control of a real
time process operation, an important requirement is the necessity of
preventing any output command from being translated into process operation
unless it is safe and desired to do so. A particular and critical control
step can be unsafe to the human operator, or it may represent a risk of
damage to the machinery, and equipment or the processed material. All such
conditions must be anticipated and the logic of control by the sequence
controller should take them into account so that only permissible output
commands are provided.
As generally known, programmable logic controllers are designed to perform
sequencing operations by first scanning signal inputs such as from relay
contacts, limit switches, pushbuttons, valves, etc., then comparing the
inputs to the conditions specified in the program and finally be
energizing or deenergizing signal outputs in accordance with the
programmed instructions. See in this respect "Programmable Logic
Controllers" by G. Lapidus, Control Engineering, April 1971, pages 49-60.
It is known also in a programmed sequence controller to advance the control
steps when machine functions, or process operations at a given step are
matched with a pattern of input conditions. In particular, the prior art
proposes logical interlocks to inhibit certain output signal functions in
the programmed sequence until certain other input signal functions have
been accomplished, and to this effect hardwiring is provided between input
conditions sensed and an AND logic operation responsive to the output
function to be abled or disabled. Seen in this regard U.S. Pat. No.
3,719,931 of R. L. Schroeder issued Mar. 6, 1973.
The prior art also shows that in sequence control apparatus is advantageous
to use a programmable matrix of logic elements, rather than hard-wired
logic, in order to modify the sequence of the control operations. See for
instance, French Pat. No. 1,493,229 granted July 17, 1967 of Siemens and
Halske A. G.
However, none of the above references is teaching the use of a separate
high-security sequencer having selected outputs so interlocked that the
propriety of outputs requested by the base programmed matrix of the
controller is tested before enabling an actual ouput command, which is one
important feature of the apparatus, system and method according to the
present invention.
The prior art also shows two sequencers interlocked by an AND logic element
to make them operate in dependency upon each other. See in this respect
U.S. Pat. No. 3,651,482 of Benson issued Mar. 21, 1972. However, the
sequencers disclosed in the Benson Patent are operating in parallel within
a common processor and interlocking does not occur in one of them.
It is also known from the U.S. Pat. No. 3,783,251 of T. M. Pavkovich issued
Jan. 1, 1974 to use two programs in digital automatic control, one program
having stored predetermined critical characteristics which are compared at
all times with the operative characteristics imposed by the other program
so that when a mismatch occurs an interlocking signal is generated to stop
the process or the machinery. Thus, one program generates a representation
of all the critical parameters not to be exceeded for safe control and it
monitors actual operation by the other program in order to detect any
operation approaching criticality. In contrast, the present invention
teaches the use of a separate high-security program having inherently safe
control characteristics, and the base program does not actually exert
control on the machine or process in relation to critical output functions
unless the instructions to be performed have been effectively taken over
by the high-security program. In addition, the present invention rather
than stopping the entire operation of the process or machinery, proposes
effective control operation in a prescribed and predetermined safe
sequential order.
It is an object of the present invention to provide a sequence controller
which is free from the prior art disadvantages and inconveniences.
Another object of the present invention is to provide a sequence controller
of simple design but increased versatility.
Still another object of the present invention is to provide a sequence
controller having selectable high-security features for application to
control of machines and processes.
SUMMARY OF THE INVENTION
The invention resides in a programmable sequence controller apparatus for
generating output commands to a controlled machine or process. The
apparatus generates a main low-security programmed sequence of requested
output signals and a high-security programmed sequence of permitted output
signals initiated by said main programmed sequence for establishing with
selected critical ones of said requested output signals said predetermined
sequence of permitted output signals in relation to process requirements
due, and means are provided gated for generating actual output commands in
response to said permitted output signals when said process requirements
are met.
The invention also resides in a method of establishing sequential output
commands to a machine or process operation and comprising the steps of:
generating a programmed sequence of requested output signals; generating a
programmed sequence of permitted output signals in accordance with
predetermined testing conditions and with at least selected critical ones
of said requested outputs and controlling said process by said permitted
output signals.
The invention further resides in a modular system for sequentially
controlling a machine or process operation including a program memory
module, a controller module, an output module, an input module and a bus
system for functionally interconnecting said modules. The programm memory
module includes a main set of stored instructions and a separate
high-security set of stored instructions. The controller module is
responsive to the main set of instructions for establishing a sequence of
requested output signals and is further responsive to said high-security
set of instructions for establishing permitted output signals in response
to selected critical ones of said requested output signals and in relation
to process requirement due. The process requirements are sensed and
translated into digital input signals. The output module is inhibited when
the controller module is operative under critical requested outputs from
the main set of instructions, but generates actual output signals in
response to said permitted output signals.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 represents an overall view of the organization of the process
sequential control system according to the present invention;
FIG. 2 is a block diagram of the sequence controller apparatus according to
the present invention showing the sequence control device and the
controller which together form the controller module in the preferred
embodiment of the present invention;
FIG. 3 shows the general organization of the sequence control device of
FIG. 2;
FIG. 4 illustrates the logic circuitry of the sequence control device used
for the generation of input and output data by the controller module of
FIG. 2 in accordance with the present invention;
FIGS. 5, 6 and 7 are logic flow charts characterizing the operation of the
sequence control device of FIGS. 3 and 4;
FIG. 8 illustrates the role of the program memory according to the present
invention in relation to critical process input conditions and requested
process commands;
FIG. 9 illustrates eight program memory cards used in the program memory
module according to the present invention;
FIG. 10 shows the internal organization of a portion of the program memory
module of FIGS. 1 and 9;
FIG. 11 shows the digital output module of FIG. 1;
FIG. 12 shows the digital input module of FIG. 1;
FIG. 13 shows the data memory and delay module of FIG. 1;
FIG. 14 is a block representation of the various modules of the sequence
control system in relation to the interlocking operation here provided;
FIG. 15 shows a logic flow chart of an illustrative low-security initiate
operation identified as INIT;
FIG. 16 shows a flow chart of an illustrative low-security main program
SCAN operation;
FIG. 17 shows a flow chart of an illustrative low-security main program
SEQUENCE ADVANCE operation;
FIG. 18 shows a logic representation of an illustrative HIGH SECURITY
program operation;
FIG. 19 is an illustrative instruction listing for the INIT program flow
chart of FIG. 15;
FIG. 20 is an illustrative instruction listing for the SCAN program of FIG.
16;
FIGS. 21A and 21B are an illustrative instruction listing for the SEQUENCE
ADVANCE program of FIG. 17;
FIG. 22 is an illustrative instruction listing for the HIGH SECURITY
program of FIG. 18; and
FIG. 23 is a block diagram depicting most generally the apparatus according
to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1 of the drawings, the overall organization of the
sequence control operation according to the present invention is shown as
a combination of several functional units in modular form arranged around
a bus system comprising: an instruction bus, a control bus, a program
address bus and a power bus. Although reference is made to one bus for
each of the connecting functions, it is well understood that each bus in
reality connects on both sides a plurality of conductors associated with
various information data to be transferred between the different modules,
with the exception, however, of the power bus since the latter does not
carry information but is used only for the supply and transport of
electrical energy from the power supply to the respective modules.
As shown in FIG. 1 the functional units include: a bus power supply module
1 connected to the power bus 2 and the control bus 3; a program memory
module 4 having connections to the instruction bus 5 and the program
address bus 6; a controller module 7 connected to the instruction bus 5
and also to the program address bus 6; a digital output module 8 operative
with the control bus 3, the program address bus 6 and the instruction bus
5; a digital input module 9 operative with the control bus 3, program
address bus 6 and instruction bus 5. The sequential control apparatus is
also provided with a data memory and delay module 10 connected to the
control bus 3 and the instruction bus 5, and an indicator module 11
operative with the control bus 3 and the instruction bus 5. It should be
observed that the power bus 2 is operative with each of the modules, as
well as the bus power supply module 1. Each of the above modules will be
described structurally and functionally hereinafter in relation to other
figures of the drawings.
As generally known, the controller module 7 responds to instructions from
the program memory 4 received over the instruction bus 5, and determines
the sequence of instructions to be addressed within the program memory 4.
Thus at any given instant, over the program address bus 6, an instruction
address is sent by the controller module 7 and a corresponding location is
selected within the program memory 4. After selection an instruction is
read out from the particular location in the memory 4 and transferred over
instruction bus 5, to be executed. Execution by the controller module 7
may consist in performing another address selection or it may involve some
datum derived from the digital input module 9, or from the data memory and
delay module 10. Execution of the instruction by the controller module 7
may require the generation of an output command by the digital output
module 8, to the outside world e.g., the controlled process. The indicator
module 11 may provide at any given time a visual representation of process
operation and of control conditions. For instance, two sets of indicators
such as described in the above referenced U.S. Pat. No. 3,719,931 of
Schroeber may be provided, if desired, which when matching would indicate
a proper correspondence between conditions required and conditions due,
and in case of a mismatch the operator would be alerted.
The controller module 7 will now be described to show some important
features of the sequence control device according to the present
invention. The program memory module 4 will be described subsequently in
order to emphasize some other important features of the controller module
7.
A. -- THE CONTROLLER MODULE
FIG. 2 schematically represents the operational relationships between the
controller module 7 and the other modules of the sequence control
apparatus according to a preferred embodiment of the present invention.
The controller module 7 includes two parts: a sequence control device 40
and a controller 41. The controller 41 will be considered separately, as
well as in the combination with the program memory module 4, or the other
functional units of the sequence control apparatus, including the sequence
control device 40.
The purpose of the sequence control device 40 is to add sophistication in
the operation of the controller 41. The sequence control device 40 will be
described first, especially to the extent of the generation of subroutine
sequences involving control commands to the controller 41, namely, and as
shown in FIGS. 2 and 3. signals for the latch return resister program,
count program, preset (or jump), reset, select, and latch instruction
register, which signals are derived on lines 42-47, respectively. Such
control operations are determined by the sequence control device 40 in
response to input condition signals appearing on lines 48-51 (shown in
FIG. 3) which pertain to respective coded signals such as F15, skip, run,
and other signals defined in the operation process which may be generated
within the controller module 7 or by some other input source. Operation of
the sequence control device 40 is determined in response to a coded
instruction of five bits F15-F11. This is the operation field of an
instruction derived on line 75 from program memory module 4. Bits F14-F11
are inputted along line 53 (shown in FIG. 3) while another line 48 is
provided as an input within the sequence control device 40 for the last
bit F15. Program memory module 4 has stored therein instructions which are
16 bits long. These include at least two parts as shown herebelow in Table
I: an operation field of five bits and an address field of ten bits.
Besides, instructions 4 to 15 include a Z field of one bit. The following
Table I illustrates 24 different types of instruction which are stored in
the program memory module 4.
TABLE I
__________________________________________________________________________
Mnemonic
Instruction Coding
Time .mu.s
Name of Instruction
__________________________________________________________________________
0 N.phi.B
00000
(not defined)
7 No-Operation; Blank
1 SRR 00001
(not defined)
9 Sub-Routine Return
2 JMP 00010
Jump Addr. Y
9 JUMP, unconditionally
3 JSR 00011
Jump Addr. Y
11 JUMP to Sub-Routine
4 IFY 00100
In. Addr. Y
Z 8 IF (Y) .noteq. Z, skip next instr.
5 STY 00101
In. Addr. Y
Z 9 STOP if (Y) = Z
6 .phi.FA
00110
Out. Addr. Y
Z 9 Output From A
7 .phi.FE
00111
Out. Addr. Y
Z 9 Output from E
8 ANA 01000
In. Addr. Y
Z 8 AND to A
9 ANB 01001
In. Addr. Y
Z 8 AND to B
10 ANC 01010
In. Addr. Y
Z 8 AND to C
11 AND 01011
In. Addr. Y
Z 8 AND to D
12 .phi.RE
01100
In. Addr. Y
Z 8 OR to E
13 .phi.RF
01101
In. Addr. Y
Z 8 OR to F
14 .phi.RG
01110
In. Addr. Y
Z 8 OR to G
15 .phi.RH
01111
In. Addr. Y
Z 8 OR to H
16 WIJ 1000 Datum Y 8 Write Immediate to J
17 WIK 1001 Datum Y 8 Write Immediate to K
18 WIL 1010 Datum Y 8 Write Immediate to L
19 WIM 1011 Datum Y 8 Write Immediate to M
20 WIN 1100 Datum Y 8 Write Immediate to N
21 WIP 1101 Datum Y 8 Write Immediate to P
22 WIR 1110 Datum Y 8 Write Immediate to R
23 N.phi.D
1111 (not defined)
8 No-Operation; Delete-Code
__________________________________________________________________________
The first 15 instructions listed are the same (F) instructions just
mentioned for controlling the sequence control device 40. The operation
field is represented by the five most significant bits, in the order
F15-F11. Thus, at a given time it is one of those 16 binary numbers which
appears on the instruction bus 5 and on line 75 leading to the sequence
control device 40.
FIG. 3 illustrates the overall organization of the sequence control device
40. It should be observed that the sequence control device 40 is organized
around a programmed memory 20 and includes a sequence counter 21, an input
unit represented by input multiplexer 55, an output unit represented by
output decode multiplexer 56, and some other generally known circuits
which relate to typical functions such as jump, enable, inhibit, store,
set, or reset, which, as well known in the art, are derived and executed
in synchronization with a clock.
The memory 20, is distinct from the main memory within program memory
module 4, and it contains 64 (2.sup.6) words of 8 bits each, of which six
bits have been reserved for the address field, and two bits for the
operation field. This memory 20 is addressed by a sequence counter 21, the
address count of which corresponds to the F14-F11 bits received on line 53
and the instructions so addressed constitute corresponding subroutines
which are read out from the memory 20 and stored in a latch register 36
gated by a clock for transferring the stored instruction to the input
multiplexer 55, or to the output decode multiplexer 56, or else (according
to the definition of the two bits in the operation field) to a "go-to (F)"
decode unit 57 or to a "UJ" (unconditional jump) decode unit 58.
Unit 57, once actuated, gates on line 18 a data selector 54, which in fact
is a 2:1 multiplexer in relation to inputs 53 and 59, where input 53
carries the F14-F11 bits, and input 59 carries a jump address. The
sequence counter 21 is gated by a load enable signal over line 60 to
receive data from line 53, or from line 59, depending upon the selection
made by the data selector 54 in response to a select signal on line 18.
When load enable signal 60 is not present, clock signal 22 causes sequence
counter 21 to be incremented. The address contained in sequence counter 21
is used to select the correponding instruction from memory 20. Reset of
the sequence counter 21 occurs by a reset signal on line 23. However, the
sequence counter of sequence control device 40 is also actuated by the
F14- F11 bits appearing on line 53 which are derived from program memory
module 4. Thus, sequence control device 40 is auxiliary to the controller
41, and in this role it performs subroutines between received successive
input (F) commands. These subroutines may involve output commands
requested to be generated, such as at the outputs 42-47 of the output
decode multiplexer 56, and they are conditioned in accordance with some
inputs, such as on lines 48-51. These input lines may be transferring an
input datum internal to the subroutine itself or the input may be a datum
derived from outside the controller module 7, as will be explained
hereafter.
Sequence control device 40 also includes an inhibit logic unit 61 which, in
response to tested conditions from the input multiplexer 55, may block via
line 62 operation of each of the four units 55, 56, 57 and 58. The
operation of the inhibit logic 61 is used to skip or not to skip the reset
instruction of the sequence control device 40. The two bits of the
operation field of the instruction generated on line 63, at any given
time, may determine which of the four units 55-58 must be controlled,
while the address field of the instruction will select the proper input or
output within the controlled unit. More particularly, the instruction
selects which input, or output, of the multiplexed unit 55, or 56, is to
be operated on.
Before considering in more detail the particular structure and operation of
the sequence control device 40 in relation to the controller unit 41 by
reference to FIG. 4, some general considerations regarding the controller
unit 41 are necessary and will be given by reference to FIG. 2.
The program counter 31 is normally incremented, as generally known, by a
count signal over line 43, and such incrementation causes the successive
instructions to be selected and read out from the program memory module 4.
The selection of addresses by the program counter is effected along line
74, (and the program address bus), into the program memory module 4. From
the program memory module 4, the selected instructions are derived (on the
instruction bus) via line 75 before being stored into an instruction
register 76 when latching occurs as controlled from line 47. When latched,
the stored instruction (which has three fields (F), (Y), (Z), as shown on
FIG. 2 and Table I) is transferred via lines 77, 88 and 78, which
respectively correspond to the (F), (Y) and (Z) fields. The (Y) field via
line 88 is gated by a data selector 79 when so selected by a select signal
appearing on line 46. As a result the program counter 31 via line 81,
assumes the (Y) address count. If the select signal on line 46 is the
opposite, the data selector 79 gates the output of return register 82, via
line 80, instead. The return register 82 stores the present address of the
program counter 31 when latched on line 42, while the contents of the next
address count in the program counter 31 are transferred via line 74.
On FIG. 4 are represented the circuits of the controller module 7 which are
associated with each of the (4 to 15) sixteen instructions listed in Table
I. These circuits are responsive to control conditioning and data signals
such as the clock signals, the Z signal on line 78, the reset signals for
the various circuits and signals representing several input data from the
main bus system, in particular those derived on the control bus 3. The
main operative elements within these circuits are the "AND" flip-flops A,
B, C and D which are represented as a unit by block 90 and the "OR"
flip-flops E, F, G and H which are represented as a unit by block 91.
Block 90 is gated by instructions such as ANA, ANB, ANC, AND which are
sent on lines 92. These may relate to one of the possible (F) commands
from line 53 (shown in FIG. 3) which are defined as shown in TABLE I.
Beside the operation field F, which is part of an instruction from the
program memory 4, there is an address field Y and a field Z. As shown in
Table I, Z is the least significant bit for instructions 4 through 15. In
fact, Z is used as a control logic to generate the complement of any given
datum. Z is derived on line 78 (see also FIG. 2), to be inputted into one
of the exclusive OR devices 93, 94 and 95. The EOR device 93 also receives
an input datum on line 96 from the control bus 3 which signal received on
line 96 is an input datum which is supplied 1) from the controlled
process, or a manual operator console, e.g., from the input module 9, 2)
from the data memory module unit 10, or 3) from one of the blocks, 90, 91,
on respective lines 97 and 98. Such input datum is transferred by the EOR
device 93 as a datum which may be stored via line 99 into one of the "AND"
flip-flop in accordance with the coded instruction ANA, ANB, ANC or AND,
appearing on line 92. If the instruction corresponds for instance to an
ANA code, (namely the ninth type of instruction in the list of Table I)
then the input datum on line 96 will be applied into the "AND" flip-flop
A, such that if this input datum is true then flip-flop A is unchanged,
but if this input datum is false, the AND flip-flop A is changed to zero.
Since flip-flop A had started out being a ONE in response to the RESET
signal on line 103, logical AND operation occurs. At the output 100 of
block 90, the datum in flip-flop A is gated by a data selector 102 as
selected by the address bits Y.sub.2 -Y.sub.1 derived on line 101 from the
instruction bus 5. This results in an input datum being transmitted on
line 97 to the control bus 3 and from there via line 96 to the controller
module, if the instruction code so dictates, to permit sensing previous
logic results during a current logic operation.
Similarly, the "OR" flip-flops E, F, G, H of block 91 may be operated upon
when gated by signals provided on line 103 in accordance with the coded
instructions .phi.RE, .phi.RF, .phi.RG, or .phi.RH. The inverted datum is
generated from the EOR device 93 via line l04, inverting circuit 105 and
106 and line 107. This results in setting a corresponding one of the OR
devices of block 91. The OR logic operation involves setting an OR
flip-flop to a ONE if the input datum is true and no action if the input
datum is false. A reset signal clears the flip-flop to a ZERO. The
non-inverted datum is impressed on block 90 via line 99. The output 108 of
block 91, as selected by data selector 109 in accordance with address bits
Y.sub.2 -Y.sub.1 (on line 110 from the instruction bus) is transmitted via
line 98 to the control bus 3.
The A and E flip-flops (but it could be any of the others if needed) serve
also the purpose of providing a first output datum on lines 111 and 113
and a second output datum on lines 112 and 114 which represent output
commands in one and in the opposite state as shown in FIG. 4. This is the
result of a combination of logic circuits including: NAND 115, for line
111 and inverter 117, coupled with NAND 116 for line 112 which are
responsive to EOR device 94 and flip-flop A, NAND 118, for line 113 and
inverter 120 coupled with NAND 119 for line 114 which are responsive to
EOR device 95 and flip-flop E. The resulting two output data on lines 111
and 112 are passed on the control bus 3 to the data memory module 10 and
the digital output module 8, as explained hereinafter.
The sequence control device 40 (FIG. 4) also includes "skip" and "run"
flip-flops represented as a unit by block 121 which is gated by
instructions IFY or STY (as defined in Table I) impressed on lines 122,
thereby to transfer datum from line 123 from the EOR device 93, and
generate skip, or run, signals on respective lines 49 and 50 which are
inputs to the input multiplexer 55 of FIG. 3. Commands "Write Immediate
Enable" may also be generated via line 24 which are performed as shown on
the code list of Table I and are transferred to the control bus 3 and from
there to the indicator module 11.
The operation of the sequence control device 40 as shown on FIGS. 3 and 4,
will now be described by reference to FIGS. 5, 6 and 7 which represent
flow charts (on FIG. 5, A through G on FIG. 6 and H through O on FIG. 9)
characterizing several typical sequences of operation.
Referring to FIG. 5, before starting any control operation the system must
have been prepared by placing all switches, all indicators, etc. in the
zero state. This is accomplished at reset system step 150, in response to
some initialize operation as indicated at 151. The next reset logic
flip-flop step 152 provides resetting of the AND flip-flops A to D in
block 90 and the OR flip-flops E to H in block 91. Step 153 indicates an
unconditional jump operation to reset step 152 from the program flow chart
shown on FIG. 6 as reset.
The sequence control apparatus having now been reset, the program advances
to step 155 to increment program counter 31. At step 156 a check is made
to see if a skip signal is provided on line 49, and if the skip logic
element is set, the answer at step 156 is YES and the command clear slip
at step 157 occurs, and the program goes back to begin at step 154 thus
skipping the execution of the current instruction. If the answer at step
156 is NO, the program goes to block 158 and calls for a latch instruction
operation, which places the reset instruction into the instruction
register 76. A check is made at step 159 to see if this instruction can be
executed (inhibit logic 61 permits execution of this instruction). If the
answer is YES the program advances to step 160, which means that the go to
F decode circuit 57 (FIG. 3) will generate a select signal on line 18 such
that data selector 54 passes the F instruction from line 53 to the
sequence counter 21. This selected F instruction determines which of the
flow chart programs of FIGS. 6 and 7 is now followed, as will be later
explained in greater detail. If the answer is NO at step 159, then at step
161, line 124 of FIG. 4 is used to transmit a write immediate enable
signal to the indicator module 11 and the program returns through being
154 to step 155.
FIGS. 6 and 7 are flow charts representing execution of the respective
first sixteen coded F instructions, listed in Table 1, each under the
assumption that the particular instruction code has been stored in as
contents of the F-Register, or instruction register 76, as expressed by
(F-Register) within the oval on the left side of each flow chart. Also, as
generally accepted in the art, the paren | | |
